blob: 40304eb5c45be9b484aacab49a6411f2afee63ba [file] [log] [blame]
Haojian Zhuang602362d2017-06-01 12:15:14 +08001/*
Haojian Zhuang1b4b4122018-01-25 16:13:05 +08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang602362d2017-06-01 12:15:14 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef PLATFORM_DEF_H
8#define PLATFORM_DEF_H
Haojian Zhuang602362d2017-06-01 12:15:14 +08009
10#include <arch.h>
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010011#include <utils_def.h>
Haojian Zhuang602362d2017-06-01 12:15:14 +080012#include "../hikey960_def.h"
13
Victor Chong2d9a42d2017-08-17 15:21:10 +090014/* Special value used to verify platform parameters from BL2 to BL3-1 */
15#define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
Haojian Zhuang602362d2017-06-01 12:15:14 +080016
17/*
18 * Generic platform constants
19 */
20
21/* Size of cacheable stacks */
Teddy Reeddd3f0a82018-09-03 17:38:50 -040022#define PLATFORM_STACK_SIZE 0x1000
Haojian Zhuang602362d2017-06-01 12:15:14 +080023
24#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
25
26#define PLATFORM_CACHE_LINE_SIZE 64
27#define PLATFORM_CLUSTER_COUNT 2
28#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
29#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
30 PLATFORM_CORE_COUNT_PER_CLUSTER)
31#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
32#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
33 PLATFORM_CLUSTER_COUNT + 1)
34
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010035#define PLAT_MAX_RET_STATE U(1)
36#define PLAT_MAX_OFF_STATE U(2)
Haojian Zhuang602362d2017-06-01 12:15:14 +080037
38#define MAX_IO_DEVICES 3
39#define MAX_IO_HANDLES 4
40/* UFS RPMB and UFS User Data */
41#define MAX_IO_BLOCK_DEVICES 2
42
43
44/*
45 * Platform memory map related constants
46 */
47
48/*
49 * BL1 specific defines.
50 */
51#define BL1_RO_BASE (0x1AC00000)
Teddy Reeddd3f0a82018-09-03 17:38:50 -040052#define BL1_RO_LIMIT (BL1_RO_BASE + 0x20000)
53#define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC2_0000 */
Haojian Zhuang602362d2017-06-01 12:15:14 +080054#define BL1_RW_SIZE (0x00188000)
55#define BL1_RW_LIMIT (0x1B000000)
56
57/*
58 * BL2 specific defines.
59 */
Haojian Zhuang1b4b4122018-01-25 16:13:05 +080060#define BL2_BASE (0x1AC00000)
61#define BL2_LIMIT (BL2_BASE + 0x58000) /* 1AC5_8000 */
Haojian Zhuang602362d2017-06-01 12:15:14 +080062
63/*
64 * BL31 specific defines.
65 */
66#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
67#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
68
Victor Chong91287682017-05-28 00:14:37 +090069/*
70 * BL3-2 specific defines.
71 */
72
73/*
74 * The TSP currently executes from TZC secured area of DRAM.
75 */
76#define BL32_DRAM_BASE DDR_SEC_BASE
77#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
78
Victor Chong7d787f52017-08-16 13:53:56 +090079#ifdef SPD_opteed
80/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
81#define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
82#define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
83#endif
Victor Chong7d787f52017-08-16 13:53:56 +090084
Victor Chong91287682017-05-28 00:14:37 +090085#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
86#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
87#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
88#define BL32_BASE BL32_DRAM_BASE
89#define BL32_LIMIT BL32_DRAM_LIMIT
90#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
91#error "SRAM storage of TSP payload is currently unsupported"
92#else
93#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
94#endif
95
Victor Chong398d5d32017-09-14 01:27:19 +090096/* BL32 is mandatory in AArch32 */
97#ifndef AARCH32
98#ifdef SPD_none
99#undef BL32_BASE
100#endif /* SPD_none */
101#endif
102
Haojian Zhuang602362d2017-06-01 12:15:14 +0800103#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
104#define NS_BL1U_SIZE (0x00100000)
105#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
106
Teddy Reeddd3f0a82018-09-03 17:38:50 -0400107#define HIKEY960_NS_IMAGE_OFFSET (0x1AC28000) /* offset in l-loader */
Haojian Zhuang602362d2017-06-01 12:15:14 +0800108#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
109
Victor Chong2d9a42d2017-08-17 15:21:10 +0900110#define SCP_BL2_BASE (0x89C80000)
111#define SCP_BL2_SIZE (0x00040000)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800112
113/*
114 * Platform specific page table and MMU setup constants
115 */
David Cunadoc1503122018-02-16 21:12:58 +0000116#define ADDR_SPACE_SIZE (1ULL << 32)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800117
Roberto Vargas82477962017-10-23 08:22:17 +0100118#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800119#define MAX_XLAT_TABLES 3
120#endif
121
Roberto Vargas82477962017-10-23 08:22:17 +0100122#ifdef IMAGE_BL2
Victor Chong7d787f52017-08-16 13:53:56 +0900123#ifdef SPD_opteed
124#define MAX_XLAT_TABLES 4
125#else
126#define MAX_XLAT_TABLES 3
127#endif
Victor Chong7d787f52017-08-16 13:53:56 +0900128#endif
129
Haojian Zhuang602362d2017-06-01 12:15:14 +0800130#define MAX_MMAP_REGIONS 16
131
132/*
133 * Declarations and constants to access the mailboxes safely. Each mailbox is
134 * aligned on the biggest cache line size in the platform. This is known only
135 * to the platform as it might have a combination of integrated and external
136 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
137 * line at any cache level. They could belong to different cpus/clusters &
138 * get written while being protected by different locks causing corruption of
139 * a valid mailbox address.
140 */
141#define CACHE_WRITEBACK_SHIFT 6
142#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
143
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100144#endif /* PLATFORM_DEF_H */