Blame - common/aarch64/early_exceptions.S - filogic/atf

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Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	1	/*
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	2	* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	3	*
				4	* Redistribution and use in source and binary forms, with or without
				5	* modification, are permitted provided that the following conditions are met:
				6	*
				7	* Redistributions of source code must retain the above copyright notice, this
				8	* list of conditions and the following disclaimer.
				9	*
				10	* Redistributions in binary form must reproduce the above copyright notice,
				11	* this list of conditions and the following disclaimer in the documentation
				12	* and/or other materials provided with the distribution.
				13	*
				14	* Neither the name of ARM nor the names of its contributors may be used
				15	* to endorse or promote products derived from this software without specific
				16	* prior written permission.
				17	*
				18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
				19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
				20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
				21	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
				22	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
				23	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
				24	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
				25	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
				26	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
				27	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
				28	* POSSIBILITY OF SUCH DAMAGE.
				29	*/
				30
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	31	#include <asm_macros.S>
Yatharth Kochar	6c0566c	2015-10-02 17:56:48 +0100	[diff] [blame]	32	#include <bl_common.h>
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	33
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	34	/* -----------------------------------------------------------------------------
				35	* Very simple stackless exception handlers used by BL2 and BL31 stages.
				36	* BL31 uses them before stacks are setup. BL2 uses them throughout.
				37	* -----------------------------------------------------------------------------
				38	*/
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	39	.globl early_exceptions
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	40
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	41	vector_base early_exceptions
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	42
				43	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	44	* Current EL with SP0 : 0x0 - 0x200
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	45	* -----------------------------------------------------
				46	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	47	vector_entry SynchronousExceptionSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	48	mov x0, #SYNC_EXCEPTION_SP_EL0
				49	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	50	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	51	check_vector_size SynchronousExceptionSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	52
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	53	vector_entry IrqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	54	mov x0, #IRQ_SP_EL0
				55	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	56	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	57	check_vector_size IrqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	58
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	59	vector_entry FiqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	60	mov x0, #FIQ_SP_EL0
				61	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	62	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	63	check_vector_size FiqSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	64
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	65	vector_entry SErrorSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	66	mov x0, #SERROR_SP_EL0
				67	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	68	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	69	check_vector_size SErrorSP0
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	70
				71	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	72	* Current EL with SPx: 0x200 - 0x400
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	73	* -----------------------------------------------------
				74	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	75	vector_entry SynchronousExceptionSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	76	mov x0, #SYNC_EXCEPTION_SP_ELX
				77	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	78	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	79	check_vector_size SynchronousExceptionSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	80
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	81	vector_entry IrqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	82	mov x0, #IRQ_SP_ELX
				83	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	84	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	85	check_vector_size IrqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	86
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	87	vector_entry FiqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	88	mov x0, #FIQ_SP_ELX
				89	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	90	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	91	check_vector_size FiqSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	92
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	93	vector_entry SErrorSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	94	mov x0, #SERROR_SP_ELX
				95	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	96	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	97	check_vector_size SErrorSPx
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	98
				99	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	100	* Lower EL using AArch64 : 0x400 - 0x600
Achin Gupta	4f6ad66	2013-10-25 09:08:21 +0100	[diff] [blame]	101	* -----------------------------------------------------
				102	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	103	vector_entry SynchronousExceptionA64
Sandrine Bailleux	4d05275	2014-03-24 10:24:08 +0000	[diff] [blame]	104	mov x0, #SYNC_EXCEPTION_AARCH64
				105	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	106	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	107	check_vector_size SynchronousExceptionA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	108
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	109	vector_entry IrqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	110	mov x0, #IRQ_AARCH64
				111	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	112	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	113	check_vector_size IrqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	114
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	115	vector_entry FiqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	116	mov x0, #FIQ_AARCH64
				117	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	118	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	119	check_vector_size FiqA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	120
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	121	vector_entry SErrorA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	122	mov x0, #SERROR_AARCH64
				123	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	124	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	125	check_vector_size SErrorA64
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	126
				127	/* -----------------------------------------------------
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	128	* Lower EL using AArch32 : 0x600 - 0x800
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	129	* -----------------------------------------------------
				130	*/
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	131	vector_entry SynchronousExceptionA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	132	mov x0, #SYNC_EXCEPTION_AARCH32
				133	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	134	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	135	check_vector_size SynchronousExceptionA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	136
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	137	vector_entry IrqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	138	mov x0, #IRQ_AARCH32
				139	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	140	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	141	check_vector_size IrqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	142
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	143	vector_entry FiqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	144	mov x0, #FIQ_AARCH32
				145	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	146	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	147	check_vector_size FiqA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	148
Sandrine Bailleux	9e6ad6c	2016-05-24 16:56:03 +0100	[diff] [blame]	149	vector_entry SErrorA32
Jeenu Viswambharan	65f0730	2014-02-07 15:50:57 +0000	[diff] [blame]	150	mov x0, #SERROR_AARCH32
				151	bl plat_report_exception
Yatharth Kochar	47b0fe3	2016-08-17 11:10:16 +0100	[diff] [blame]	152	bl plat_panic_handler
Jeenu Viswambharan	a7934d6	2014-02-07 15:53:18 +0000	[diff] [blame]	153	check_vector_size SErrorA32