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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __CSS_DEF_H__
32#define __CSS_DEF_H__
33
34#include <arm_def.h>
35#include <tzc400.h>
36
37/*************************************************************************
38 * Definitions common to all ARM Compute SubSystems (CSS)
39 *************************************************************************/
Dan Handley9df48042015-03-19 18:58:55 +000040#define NSROM_BASE 0x1f000000
41#define NSROM_SIZE 0x00001000
42
43/* Following covers CSS Peripherals excluding NSROM and NSRAM */
44#define CSS_DEVICE_BASE 0x20000000
45#define CSS_DEVICE_SIZE 0x0e000000
Dan Handley9df48042015-03-19 18:58:55 +000046
47#define NSRAM_BASE 0x2e000000
48#define NSRAM_SIZE 0x00008000
49
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010050/* System Security Control Registers */
51#define SSC_REG_BASE 0x2a420000
52#define SSC_GPRETN (SSC_REG_BASE + 0x030)
53
Dan Handley9df48042015-03-19 18:58:55 +000054/* The slave_bootsecure controls access to GPU, DMC and CS. */
55#define CSS_NIC400_SLAVE_BOOTSECURE 8
56
57/* Interrupt handling constants */
58#define CSS_IRQ_MHU 69
59#define CSS_IRQ_GPU_SMMU_0 71
Dan Handley9df48042015-03-19 18:58:55 +000060#define CSS_IRQ_TZC 80
61#define CSS_IRQ_TZ_WDOG 86
Vikram Kanigirif3bcea22015-06-24 17:51:09 +010062#define CSS_IRQ_SEC_SYS_TIMER 91
Dan Handley9df48042015-03-19 18:58:55 +000063
Sandrine Bailleux761bba32015-04-29 13:02:46 +010064/*
Achin Gupta1fa7eb62015-11-03 14:18:34 +000065 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a
66 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts.
67 */
68#define CSS_G1S_IRQS CSS_IRQ_MHU, \
69 CSS_IRQ_GPU_SMMU_0, \
70 CSS_IRQ_TZC, \
71 CSS_IRQ_TZ_WDOG, \
72 CSS_IRQ_SEC_SYS_TIMER
73
74/*
Sandrine Bailleux761bba32015-04-29 13:02:46 +010075 * SCP <=> AP boot configuration
76 *
77 * The SCP/AP boot configuration is a 32-bit word located at a known offset from
Vikram Kanigiri72084192016-02-08 16:29:30 +000078 * the start of the Trusted SRAM.
Sandrine Bailleux761bba32015-04-29 13:02:46 +010079 *
80 * Note that the value stored at this address is only valid at boot time, before
Juan Castilloa72b6472015-12-10 15:49:17 +000081 * the SCP_BL2 image is transferred to SCP.
Sandrine Bailleux761bba32015-04-29 13:02:46 +010082 */
Vikram Kanigiri72084192016-02-08 16:29:30 +000083#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
Dan Handley9df48042015-03-19 18:58:55 +000084
85#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
86 CSS_DEVICE_BASE, \
87 CSS_DEVICE_SIZE, \
88 MT_DEVICE | MT_RW | MT_SECURE)
89
Vikram Kanigirif79d1502015-11-12 17:22:16 +000090/* Platform ID address */
91#define SSC_VERSION_OFFSET 0x040
92
93#define SSC_VERSION_CONFIG_SHIFT 28
94#define SSC_VERSION_MAJOR_REV_SHIFT 24
95#define SSC_VERSION_MINOR_REV_SHIFT 20
96#define SSC_VERSION_DESIGNER_ID_SHIFT 12
97#define SSC_VERSION_PART_NUM_SHIFT 0x0
98#define SSC_VERSION_CONFIG_MASK 0xf
99#define SSC_VERSION_MAJOR_REV_MASK 0xf
100#define SSC_VERSION_MINOR_REV_MASK 0xf
101#define SSC_VERSION_DESIGNER_ID_MASK 0xff
102#define SSC_VERSION_PART_NUM_MASK 0xfff
103
104#ifndef __ASSEMBLY__
105
106/* SSC_VERSION related accessors */
107
108/* Returns the part number of the platform */
109#define GET_SSC_VERSION_PART_NUM(val) \
110 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \
111 SSC_VERSION_PART_NUM_MASK)
112
113/* Returns the configuration number of the platform */
114#define GET_SSC_VERSION_CONFIG(val) \
115 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \
116 SSC_VERSION_CONFIG_MASK)
117
118#endif /* __ASSEMBLY__ */
Dan Handley9df48042015-03-19 18:58:55 +0000119
120/*************************************************************************
121 * Required platform porting definitions common to all
122 * ARM Compute SubSystems (CSS)
123 ************************************************************************/
124
125/*
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000126 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there
127 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE).
128 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load
129 * an SCP_BL2/SCP_BL2U image.
130 */
131#if CSS_LOAD_SCP_IMAGES
132/*
Juan Castilloa72b6472015-12-10 15:49:17 +0000133 * Load address of SCP_BL2 in CSS platform ports
Juan Castillo7d199412015-12-14 09:35:25 +0000134 * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the
135 * SCP, it is discarded and BL31 is loaded over the top.
Dan Handley9df48042015-03-19 18:58:55 +0000136 */
Juan Castilloa72b6472015-12-10 15:49:17 +0000137#define SCP_BL2_BASE BL31_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000138
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100139#define SCP_BL2U_BASE BL31_BASE
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000140#endif /* CSS_LOAD_SCP_IMAGES */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100141
Dan Handley9df48042015-03-19 18:58:55 +0000142/* Load address of Non-Secure Image for CSS platform ports */
143#define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000
144
145/* TZC related constants */
Soby Mathew9c708b52016-02-26 14:23:19 +0000146#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
Vikram Kanigiria2cee032015-07-31 16:35:05 +0100147
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100148/* Trusted mailbox base address common to all CSS */
149#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
150
151
Dan Handley9df48042015-03-19 18:58:55 +0000152#endif /* __CSS_DEF_H__ */