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git01.mediatek.com / filogic / atf / 88040b53f81f87405a1308afbd5cddf0a059af18 / . / plat / ti / k3 / common / plat_common.mk
blob: c91a03586fe55c1ba782007017315776d852500e [file] [log] [blame]
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]1#
2# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# We don't use BL1 or BL2, so BL31 is the first image to execute
8RESET_TO_BL31 := 1
9# Only one core starts up at first
10COLD_BOOT_SINGLE_CPU := 1
11# We can choose where a core starts executing
12PROGRAMMABLE_RESET_ADDRESS:= 1
13
14# System coherency is managed in hardware
Andrew F. Davis7c461d72018-10-12 15:37:04 -0500[diff] [blame]15HW_ASSISTED_COHERENCY := 1
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]16USE_COHERENT_MEM := 0
17
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]18# A53 erratum for SoC. (enable them all)
19ERRATA_A53_826319 := 1
20ERRATA_A53_835769 := 1
21ERRATA_A53_836870 := 1
22ERRATA_A53_843419 := 1
23ERRATA_A53_855873 := 1
24
Andrew F. Davis7c461d72018-10-12 15:37:04 -0500[diff] [blame]25# Leave the caches enabled on core powerdown path
26TI_AM65X_WORKAROUND := 1
27$(eval $(call add_define,TI_AM65X_WORKAROUND))
28
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]29MULTI_CONSOLE_API := 1
30TI_16550_MDR_QUIRK := 1
31$(eval $(call add_define,TI_16550_MDR_QUIRK))
32
Andreas Dannenberg5e6d1402019-01-14 13:20:15 -0600[diff] [blame]33# Allow customizing the UART baud rate
34K3_USART_BAUD := 115200
35$(eval $(call add_define,K3_USART_BAUD))
36
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000[diff] [blame]37# Libraries
38include lib/xlat_tables_v2/xlat_tables.mk
39
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]40PLAT_INCLUDES += \
41 -I${PLAT_PATH}/include \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]42 -I${PLAT_PATH}/common/drivers/sec_proxy \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]43 -I${PLAT_PATH}/common/drivers/ti_sci \
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]44
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]45K3_CONSOLE_SOURCES += \
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]46 drivers/ti/uart/aarch64/16550_console.S \
47 ${PLAT_PATH}/common/k3_console.c \
48
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]49K3_GIC_SOURCES += \
50 drivers/arm/gic/common/gic_common.c \
51 drivers/arm/gic/v3/gicv3_main.c \
52 drivers/arm/gic/v3/gicv3_helpers.c \
53 plat/common/plat_gicv3.c \
54 ${PLAT_PATH}/common/k3_gicv3.c \
55
Benjamin Faira42b61b2016-10-14 01:13:46 +0000[diff] [blame]56K3_PSCI_SOURCES += \
57 plat/common/plat_psci_common.c \
58 ${PLAT_PATH}/common/k3_psci.c \
59
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]60K3_SEC_PROXY_SOURCES += \
61 ${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
62
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]63K3_TI_SCI_SOURCES += \
64 ${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
65
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]66PLAT_BL_COMMON_SOURCES += \
67 lib/cpus/aarch64/cortex_a53.S \
Nishanth Menon3ed1b282016-10-14 01:13:45 +0000[diff] [blame]68 ${XLAT_TABLES_LIB_SRCS} \
Nishanth Menonce976042016-10-14 01:13:44 +0000[diff] [blame]69 ${K3_CONSOLE_SOURCES} \
Nishanth Menon0192f892016-10-14 01:13:34 +0000[diff] [blame]70
71BL31_SOURCES += \
72 ${PLAT_PATH}/common/k3_bl31_setup.c \
Benjamin Fairf807a342016-10-18 14:32:06 -0500[diff] [blame]73 ${PLAT_PATH}/common/k3_helpers.S \
Benjamin Fair42eea872016-10-14 01:13:47 +0000[diff] [blame]74 ${PLAT_PATH}/common/k3_topology.c \
Nishanth Menonf97ad372016-10-14 01:13:49 +0000[diff] [blame]75 ${K3_GIC_SOURCES} \
Benjamin Faira42b61b2016-10-14 01:13:46 +0000[diff] [blame]76 ${K3_PSCI_SOURCES} \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +0000[diff] [blame]77 ${K3_SEC_PROXY_SOURCES} \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +0000[diff] [blame]78 ${K3_TI_SCI_SOURCES} \