Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 1 | /* |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 2 | * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/bl_common.h> |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 10 | #include <cortex_a35.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* --------------------------------------------- |
| 15 | * Disable L1 data cache and unified L2 cache |
| 16 | * --------------------------------------------- |
| 17 | */ |
| 18 | func cortex_a35_disable_dcache |
Sona Mathew | cfc66a5 | 2023-06-19 14:49:02 -0500 | [diff] [blame] | 19 | sysreg_bit_clear sctlr_el3, SCTLR_C_BIT |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 20 | isb |
| 21 | ret |
| 22 | endfunc cortex_a35_disable_dcache |
| 23 | |
| 24 | /* --------------------------------------------- |
| 25 | * Disable intra-cluster coherency |
| 26 | * --------------------------------------------- |
| 27 | */ |
| 28 | func cortex_a35_disable_smp |
Sona Mathew | cfc66a5 | 2023-06-19 14:49:02 -0500 | [diff] [blame] | 29 | sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 30 | isb |
| 31 | dsb sy |
| 32 | ret |
| 33 | endfunc cortex_a35_disable_smp |
| 34 | |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 35 | workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472 |
Sona Mathew | cfc66a5 | 2023-06-19 14:49:02 -0500 | [diff] [blame] | 36 | sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 37 | workaround_reset_end cortex_a35, ERRATUM(855472) |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 38 | |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 39 | check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0) |
Louis Mayencourt | 8a06127 | 2019-04-05 16:25:25 +0100 | [diff] [blame] | 40 | |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 41 | /* ------------------------------------------------- |
| 42 | * The CPU Ops reset function for Cortex-A35. |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 43 | * ------------------------------------------------- |
| 44 | */ |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 45 | cpu_reset_func_start cortex_a35 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 46 | /* --------------------------------------------- |
Sandrine Bailleux | f12a31d | 2016-01-29 14:37:58 +0000 | [diff] [blame] | 47 | * Enable the SMP bit. |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 48 | * --------------------------------------------- |
| 49 | */ |
Sona Mathew | cfc66a5 | 2023-06-19 14:49:02 -0500 | [diff] [blame] | 50 | sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 51 | cpu_reset_func_end cortex_a35 |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 52 | |
| 53 | func cortex_a35_core_pwr_dwn |
| 54 | mov x18, x30 |
| 55 | |
| 56 | /* --------------------------------------------- |
| 57 | * Turn off caches. |
| 58 | * --------------------------------------------- |
| 59 | */ |
| 60 | bl cortex_a35_disable_dcache |
| 61 | |
| 62 | /* --------------------------------------------- |
| 63 | * Flush L1 caches. |
| 64 | * --------------------------------------------- |
| 65 | */ |
| 66 | mov x0, #DCCISW |
| 67 | bl dcsw_op_level1 |
| 68 | |
| 69 | /* --------------------------------------------- |
| 70 | * Come out of intra cluster coherency |
| 71 | * --------------------------------------------- |
| 72 | */ |
| 73 | mov x30, x18 |
| 74 | b cortex_a35_disable_smp |
| 75 | endfunc cortex_a35_core_pwr_dwn |
| 76 | |
| 77 | func cortex_a35_cluster_pwr_dwn |
| 78 | mov x18, x30 |
| 79 | |
| 80 | /* --------------------------------------------- |
| 81 | * Turn off caches. |
| 82 | * --------------------------------------------- |
| 83 | */ |
| 84 | bl cortex_a35_disable_dcache |
| 85 | |
| 86 | /* --------------------------------------------- |
| 87 | * Flush L1 caches. |
| 88 | * --------------------------------------------- |
| 89 | */ |
| 90 | mov x0, #DCCISW |
| 91 | bl dcsw_op_level1 |
| 92 | |
| 93 | /* --------------------------------------------- |
| 94 | * Disable the optional ACP. |
| 95 | * --------------------------------------------- |
| 96 | */ |
| 97 | bl plat_disable_acp |
| 98 | |
| 99 | /* --------------------------------------------- |
| 100 | * Flush L2 caches. |
| 101 | * --------------------------------------------- |
| 102 | */ |
| 103 | mov x0, #DCCISW |
| 104 | bl dcsw_op_level2 |
| 105 | |
| 106 | /* --------------------------------------------- |
| 107 | * Come out of intra cluster coherency |
| 108 | * --------------------------------------------- |
| 109 | */ |
| 110 | mov x30, x18 |
| 111 | b cortex_a35_disable_smp |
| 112 | endfunc cortex_a35_cluster_pwr_dwn |
| 113 | |
Sona Mathew | 92c0aa8 | 2023-06-19 14:43:43 -0500 | [diff] [blame] | 114 | errata_report_shim cortex_a35 |
Soby Mathew | 0980dce | 2018-09-17 04:34:35 +0100 | [diff] [blame] | 115 | |
Sandrine Bailleux | 432aa77 | 2016-01-07 16:52:49 +0000 | [diff] [blame] | 116 | /* --------------------------------------------- |
| 117 | * This function provides cortex_a35 specific |
| 118 | * register information for crash reporting. |
| 119 | * It needs to return with x6 pointing to |
| 120 | * a list of register names in ascii and |
| 121 | * x8 - x15 having values of registers to be |
| 122 | * reported. |
| 123 | * --------------------------------------------- |
| 124 | */ |
| 125 | .section .rodata.cortex_a35_regs, "aS" |
| 126 | cortex_a35_regs: /* The ascii list of register names to be reported */ |
| 127 | .asciz "cpuectlr_el1", "" |
| 128 | |
| 129 | func cortex_a35_cpu_reg_dump |
| 130 | adr x6, cortex_a35_regs |
| 131 | mrs x8, CORTEX_A35_CPUECTLR_EL1 |
| 132 | ret |
| 133 | endfunc cortex_a35_cpu_reg_dump |
| 134 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 135 | declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \ |
| 136 | cortex_a35_reset_func, \ |
| 137 | cortex_a35_core_pwr_dwn, \ |
| 138 | cortex_a35_cluster_pwr_dwn |