Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 1 | /* |
Stephan Gerhold | a0ab8da | 2023-04-06 21:43:37 +0200 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | |
| 10 | #include <msm8916_mmap.h> |
| 11 | |
| 12 | #define APCS_TCM_START_ADDR 0x10 |
| 13 | #define APCS_TCM_REDIRECT_EN_0 BIT_32(0) |
| 14 | |
| 15 | .globl plat_crash_console_init |
| 16 | .globl plat_crash_console_putc |
| 17 | .globl plat_crash_console_flush |
| 18 | .globl plat_panic_handler |
| 19 | .globl plat_my_core_pos |
| 20 | .globl plat_get_my_entrypoint |
| 21 | .globl plat_reset_handler |
| 22 | .globl platform_mem_init |
| 23 | .globl msm8916_entry_point |
| 24 | |
| 25 | /* ------------------------------------------------- |
| 26 | * int plat_crash_console_init(void) |
| 27 | * Initialize the crash console. |
| 28 | * Out: x0 - 1 on success, 0 on error |
| 29 | * Clobber list : x0 - x4 |
| 30 | * ------------------------------------------------- |
| 31 | */ |
| 32 | func plat_crash_console_init |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 33 | mov_imm x1, BLSP_UART_BASE |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 34 | mov x0, #1 |
| 35 | b console_uartdm_core_init |
| 36 | endfunc plat_crash_console_init |
| 37 | |
| 38 | /* ------------------------------------------------- |
| 39 | * int plat_crash_console_putc(int c) |
| 40 | * Print a character on the crash console. |
| 41 | * In : w0 - character to be printed |
| 42 | * Out: w0 - printed character on success |
| 43 | * Clobber list : x1, x2 |
| 44 | * ------------------------------------------------- |
| 45 | */ |
| 46 | func plat_crash_console_putc |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 47 | mov_imm x1, BLSP_UART_BASE |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 48 | b console_uartdm_core_putc |
| 49 | endfunc plat_crash_console_putc |
| 50 | |
| 51 | /* ------------------------------------------------- |
| 52 | * void plat_crash_console_flush(void) |
| 53 | * Force a write of all buffered data that has not |
| 54 | * been output. |
| 55 | * Clobber list : x1, x2 |
| 56 | * ------------------------------------------------- |
| 57 | */ |
| 58 | func plat_crash_console_flush |
Stephan Gerhold | 71939dd | 2022-09-02 23:29:17 +0200 | [diff] [blame] | 59 | mov_imm x1, BLSP_UART_BASE |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 60 | b console_uartdm_core_flush |
| 61 | endfunc plat_crash_console_flush |
| 62 | |
| 63 | /* ------------------------------------------------- |
| 64 | * void plat_panic_handler(void) __dead |
| 65 | * Called when an unrecoverable error occurs. |
| 66 | * ------------------------------------------------- |
| 67 | */ |
| 68 | func plat_panic_handler |
| 69 | /* Try to shutdown/reset */ |
| 70 | mov_imm x0, MPM_PS_HOLD |
| 71 | str wzr, [x0] |
| 72 | 1: b 1b |
| 73 | endfunc plat_panic_handler |
| 74 | |
| 75 | /* ------------------------------------------------- |
| 76 | * unsigned int plat_my_core_pos(void) |
| 77 | * Out: x0 - index of the calling CPU |
| 78 | * ------------------------------------------------- |
| 79 | */ |
| 80 | func plat_my_core_pos |
| 81 | /* There is just a single cluster so this is very simple */ |
| 82 | mrs x0, mpidr_el1 |
| 83 | and x0, x0, #MPIDR_CPU_MASK |
| 84 | ret |
| 85 | endfunc plat_my_core_pos |
| 86 | |
| 87 | /* ------------------------------------------------- |
| 88 | * uintptr_t plat_get_my_entrypoint(void) |
| 89 | * Distinguish cold and warm boot and return warm boot |
| 90 | * entry address if available. |
| 91 | * Out: x0 - warm boot entry point or 0 on cold boot |
| 92 | * ------------------------------------------------- |
| 93 | */ |
| 94 | func plat_get_my_entrypoint |
| 95 | ldr x0, msm8916_entry_point |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 96 | cbz x0, 1f |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 97 | ret |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 98 | 1: |
| 99 | /* |
| 100 | * Cold boot: Disable TCM redirect to L2 cache as early as |
| 101 | * possible to avoid crashes when making use of the cache. |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 102 | */ |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 103 | mov_imm x1, APCS_CFG |
| 104 | ldr w2, [x1, #APCS_TCM_START_ADDR] |
| 105 | and w2, w2, #~APCS_TCM_REDIRECT_EN_0 |
| 106 | str w2, [x1, #APCS_TCM_START_ADDR] |
| 107 | |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 108 | /* |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 109 | * After reset the CPU always starts executing at the fixed reset |
| 110 | * address (0x0), which does not match the link address of BL31. |
| 111 | * The "boot remapper" redirects all memory accesses to the real |
| 112 | * physical address in DRAM. |
| 113 | * |
| 114 | * For warm boots, this is already handled by loading the real |
| 115 | * entry point address above. |
| 116 | * |
| 117 | * For cold boots, check if the CPU is using the boot remapper, |
| 118 | * i.e. if bl31_entrypoint appears to be at the reset address (0x0). |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 119 | */ |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 120 | adr x1, bl31_entrypoint |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 121 | cbnz x1, 2f |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 122 | |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 123 | /* |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 124 | * Add the real BL31_BASE offset to the return address in the link |
| 125 | * register so the CPU will continue at the real address after return. |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 126 | */ |
Stephan Gerhold | fe45fa8 | 2023-04-17 15:55:27 +0200 | [diff] [blame] | 127 | mov_imm x1, BL31_BASE |
| 128 | add lr, lr, x1 |
| 129 | 2: |
| 130 | ret |
| 131 | endfunc plat_get_my_entrypoint |
Stephan Gerhold | 14fdf07 | 2021-12-01 20:01:11 +0100 | [diff] [blame] | 132 | |
| 133 | /* ------------------------------------------------- |
| 134 | * void platform_mem_init(void) |
| 135 | * Performs additional memory initialization early |
| 136 | * in the boot process. |
| 137 | * ------------------------------------------------- |
| 138 | */ |
| 139 | func platform_mem_init |
| 140 | /* Nothing to do here, all memory is already initialized */ |
| 141 | ret |
| 142 | endfunc platform_mem_init |
| 143 | |
| 144 | .data |
| 145 | .align 3 |
| 146 | |
| 147 | /* ------------------------------------------------- |
| 148 | * Warm boot entry point for CPU. Set by PSCI code. |
| 149 | * ------------------------------------------------- |
| 150 | */ |
| 151 | msm8916_entry_point: |
| 152 | .quad 0 |