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Olivier Deprezecb2fe52020-04-02 15:38:02 +02001Secure Partition Manager
2************************
3
4.. contents::
5
6Acronyms
7========
8
Olivier Deprez2b0be752021-09-01 10:25:21 +02009+--------+--------------------------------------+
10| CoT | Chain of Trust |
11+--------+--------------------------------------+
12| DMA | Direct Memory Access |
13+--------+--------------------------------------+
14| DTB | Device Tree Blob |
15+--------+--------------------------------------+
16| DTS | Device Tree Source |
17+--------+--------------------------------------+
18| EC | Execution Context |
19+--------+--------------------------------------+
20| FIP | Firmware Image Package |
21+--------+--------------------------------------+
22| FF-A | Firmware Framework for Arm A-profile |
23+--------+--------------------------------------+
24| IPA | Intermediate Physical Address |
25+--------+--------------------------------------+
26| NWd | Normal World |
27+--------+--------------------------------------+
28| ODM | Original Design Manufacturer |
29+--------+--------------------------------------+
30| OEM | Original Equipment Manufacturer |
31+--------+--------------------------------------+
32| PA | Physical Address |
33+--------+--------------------------------------+
34| PE | Processing Element |
35+--------+--------------------------------------+
36| PM | Power Management |
37+--------+--------------------------------------+
38| PVM | Primary VM |
39+--------+--------------------------------------+
40| SMMU | System Memory Management Unit |
41+--------+--------------------------------------+
42| SP | Secure Partition |
43+--------+--------------------------------------+
44| SPD | Secure Payload Dispatcher |
45+--------+--------------------------------------+
46| SPM | Secure Partition Manager |
47+--------+--------------------------------------+
48| SPMC | SPM Core |
49+--------+--------------------------------------+
50| SPMD | SPM Dispatcher |
51+--------+--------------------------------------+
52| SiP | Silicon Provider |
53+--------+--------------------------------------+
54| SWd | Secure World |
55+--------+--------------------------------------+
56| TLV | Tag-Length-Value |
57+--------+--------------------------------------+
58| TOS | Trusted Operating System |
59+--------+--------------------------------------+
60| VM | Virtual Machine |
61+--------+--------------------------------------+
Olivier Deprezecb2fe52020-04-02 15:38:02 +020062
63Foreword
64========
65
66Two implementations of a Secure Partition Manager co-exist in the TF-A codebase:
67
Olivier Deprez5e0a73f2021-04-30 14:42:24 +020068- SPM based on the FF-A specification `[1]`_.
69- SPM based on the MM interface to communicate with an S-EL0 partition `[2]`_.
Olivier Deprezecb2fe52020-04-02 15:38:02 +020070
71Both implementations differ in their architectures and only one can be selected
72at build time.
73
74This document:
75
Olivier Deprez5e0a73f2021-04-30 14:42:24 +020076- describes the FF-A implementation where the Secure Partition Manager
77 resides at EL3 and S-EL2 (or EL3 and S-EL1).
78- is not an architecture specification and it might provide assumptions
79 on sections mandated as implementation-defined in the specification.
80- covers the implications to TF-A used as a bootloader, and Hafnium
81 used as a reference code base for an S-EL2 secure firmware on
82 platforms implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2)
83 architecture extension.
Olivier Deprezecb2fe52020-04-02 15:38:02 +020084
85Terminology
86-----------
87
Olivier Deprez5e0a73f2021-04-30 14:42:24 +020088- The term Hypervisor refers to the NS-EL2 component managing Virtual Machines
89 (or partitions) in the normal world.
90- The term SPMC refers to the S-EL2 component managing secure partitions in
91 the secure world when the FEAT_SEL2 architecture extension is implemented.
92- Alternatively, SPMC can refer to an S-EL1 component, itself being a secure
93 partition and implementing the FF-A ABI on platforms not implementing the
94 FEAT_SEL2 architecture extension.
95- The term VM refers to a normal world Virtual Machine managed by an Hypervisor.
96- The term SP refers to a secure world "Virtual Machine" managed by an SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +020097
98Support for legacy platforms
99----------------------------
100
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200101In the implementation, the SPM is split into SPMD and SPMC components.
102The SPMD is located at EL3 and mainly relays FF-A messages from
103NWd (Hypervisor or OS kernel) to SPMC located either at S-EL1 or S-EL2.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200104
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200105Hence TF-A supports both cases where the SPMC is located either at:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200106
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200107- S-EL1 supporting platforms not implementing the FEAT_SEL2 architecture
108 extension. The SPMD relays the FF-A protocol from EL3 to S-EL1.
109- or S-EL2 supporting platforms implementing the FEAT_SEL2 architecture
110 extension. The SPMD relays the FF-A protocol from EL3 to S-EL2.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200111
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200112The same TF-A SPMD component is used to support both configurations.
113The SPMC exception level is a build time choice.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200114
115Sample reference stack
116======================
117
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200118The following diagram illustrates a possible configuration when the
119FEAT_SEL2 architecture extension is implemented, showing the SPMD
120and SPMC, one or multiple secure partitions, with an optional
121Hypervisor:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200122
123.. image:: ../resources/diagrams/ff-a-spm-sel2.png
124
125TF-A build options
126==================
127
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200128This section explains the TF-A build options involved in building with
129support for an FF-A based SPM where the SPMD is located at EL3 and the
130SPMC located at S-EL1 or S-EL2:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200131
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200132- **SPD=spmd**: this option selects the SPMD component to relay the FF-A
133 protocol from NWd to SWd back and forth. It is not possible to
134 enable another Secure Payload Dispatcher when this option is chosen.
135- **SPMD_SPM_AT_SEL2**: this option adjusts the SPMC exception
136 level to being S-EL1 or S-EL2. It defaults to enabled (value 1) when
137 SPD=spmd is chosen.
138- **CTX_INCLUDE_EL2_REGS**: this option permits saving (resp.
139 restoring) the EL2 system register context before entering (resp.
140 after leaving) the SPMC. It is mandatorily enabled when
141 ``SPMD_SPM_AT_SEL2`` is enabled. The context save/restore routine
142 and exhaustive list of registers is visible at `[4]`_.
143- **SP_LAYOUT_FILE**: this option specifies a text description file
144 providing paths to SP binary images and manifests in DTS format
145 (see `Describing secure partitions`_). It
146 is required when ``SPMD_SPM_AT_SEL2`` is enabled hence when multiple
147 secure partitions are to be loaded on behalf of the SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200148
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200149+---------------+----------------------+------------------+
150| | CTX_INCLUDE_EL2_REGS | SPMD_SPM_AT_SEL2 |
151+---------------+----------------------+------------------+
152| SPMC at S-EL1 | 0 | 0 |
153+---------------+----------------------+------------------+
154| SPMC at S-EL2 | 1 | 1 (default when |
155| | | SPD=spmd) |
156+---------------+----------------------+------------------+
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200157
158Other combinations of such build options either break the build or are not
159supported.
160
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200161Notes:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200162
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200163- Only Arm's FVP platform is supported to use with the TF-A reference software
164 stack.
165- The reference software stack uses FEAT_PAuth (formerly Armv8.3-PAuth) and
166 FEAT_BTI (formerly Armv8.5-BTI) architecture extensions by default at EL3
167 and S-EL2.
168- The ``CTX_INCLUDE_EL2_REGS`` option provides the generic support for
169 barely saving/restoring EL2 registers from an Arm arch perspective. As such
170 it is decoupled from the ``SPD=spmd`` option.
171- BL32 option is re-purposed to specify the SPMC image. It can specify either
172 the Hafnium binary path (built for the secure world) or the path to a TEE
173 binary implementing FF-A interfaces.
174- BL33 option can specify the TFTF binary or a normal world loader
175 such as U-Boot or the UEFI framework.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200176
177Sample TF-A build command line when SPMC is located at S-EL1
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200178(e.g. when the FEAT_EL2 architecture extension is not implemented):
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200179
180.. code:: shell
181
182 make \
183 CROSS_COMPILE=aarch64-none-elf- \
184 SPD=spmd \
185 SPMD_SPM_AT_SEL2=0 \
186 BL32=<path-to-tee-binary> \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200187 BL33=<path-to-bl33-binary> \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200188 PLAT=fvp \
189 all fip
190
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200191Sample TF-A build command line for a FEAT_SEL2 enabled system where the SPMC is
192located at S-EL2:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200193
194.. code:: shell
195
196 make \
197 CROSS_COMPILE=aarch64-none-elf- \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200198 PLAT=fvp \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200199 SPD=spmd \
200 CTX_INCLUDE_EL2_REGS=1 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200201 ARM_ARCH_MINOR=5 \
202 BRANCH_PROTECTION=1 \
203 CTX_INCLUDE_PAUTH_REGS=1 \
204 BL32=<path-to-hafnium-binary> \
205 BL33=<path-to-bl33-binary> \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200206 SP_LAYOUT_FILE=sp_layout.json \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200207 all fip
208
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200209Same as above with enabling secure boot in addition:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200210
211.. code:: shell
212
213 make \
214 CROSS_COMPILE=aarch64-none-elf- \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200215 PLAT=fvp \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200216 SPD=spmd \
217 CTX_INCLUDE_EL2_REGS=1 \
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200218 ARM_ARCH_MINOR=5 \
219 BRANCH_PROTECTION=1 \
220 CTX_INCLUDE_PAUTH_REGS=1 \
221 BL32=<path-to-hafnium-binary> \
222 BL33=<path-to-bl33-binary> \
223 SP_LAYOUT_FILE=sp_layout.json \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200224 MBEDTLS_DIR=<path-to-mbedtls-lib> \
225 TRUSTED_BOARD_BOOT=1 \
226 COT=dualroot \
227 ARM_ROTPK_LOCATION=devel_rsa \
228 ROT_KEY=plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem \
229 GENERATE_COT=1 \
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200230 all fip
231
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200232FVP model invocation
233====================
234
235The FVP command line needs the following options to exercise the S-EL2 SPMC:
236
237+---------------------------------------------------+------------------------------------+
238| - cluster0.has_arm_v8-5=1 | Implements FEAT_SEL2, FEAT_PAuth, |
239| - cluster1.has_arm_v8-5=1 | and FEAT_BTI. |
240+---------------------------------------------------+------------------------------------+
241| - pci.pci_smmuv3.mmu.SMMU_AIDR=2 | Parameters required for the |
242| - pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B | SMMUv3.2 modeling. |
243| - pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 | |
244| - pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 | |
245| - pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 | |
246| - pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 | |
247| - pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 | |
248| - pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 | |
249+---------------------------------------------------+------------------------------------+
250| - cluster0.has_branch_target_exception=1 | Implements FEAT_BTI. |
251| - cluster1.has_branch_target_exception=1 | |
252+---------------------------------------------------+------------------------------------+
253| - cluster0.restriction_on_speculative_execution=2 | Required by the EL2 context |
254| - cluster1.restriction_on_speculative_execution=2 | save/restore routine. |
255+---------------------------------------------------+------------------------------------+
256
257Sample FVP command line invocation:
258
259.. code:: shell
260
261 <path-to-fvp-model>/FVP_Base_RevC-2xAEMv8A -C pctl.startup=0.0.0.0
262 -C cluster0.NUM_CORES=4 -C cluster1.NUM_CORES=4 -C bp.secure_memory=1 \
263 -C bp.secureflashloader.fname=trusted-firmware-a/build/fvp/debug/bl1.bin \
264 -C bp.flashloader0.fname=trusted-firmware-a/build/fvp/debug/fip.bin \
265 -C bp.pl011_uart0.out_file=fvp-uart0.log -C bp.pl011_uart1.out_file=fvp-uart1.log \
266 -C bp.pl011_uart2.out_file=fvp-uart2.log \
267 -C cluster0.has_arm_v8-5=1 -C cluster1.has_arm_v8-5=1 -C pci.pci_smmuv3.mmu.SMMU_AIDR=2 \
268 -C pci.pci_smmuv3.mmu.SMMU_IDR0=0x0046123B -C pci.pci_smmuv3.mmu.SMMU_IDR1=0x00600002 \
269 -C pci.pci_smmuv3.mmu.SMMU_IDR3=0x1714 -C pci.pci_smmuv3.mmu.SMMU_IDR5=0xFFFF0472 \
270 -C pci.pci_smmuv3.mmu.SMMU_S_IDR1=0xA0000002 -C pci.pci_smmuv3.mmu.SMMU_S_IDR2=0 \
271 -C pci.pci_smmuv3.mmu.SMMU_S_IDR3=0 \
272 -C cluster0.has_branch_target_exception=1 \
273 -C cluster1.has_branch_target_exception=1 \
274 -C cluster0.restriction_on_speculative_execution=2 \
275 -C cluster1.restriction_on_speculative_execution=2
276
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200277Boot process
278============
279
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200280Loading Hafnium and secure partitions in the secure world
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200281---------------------------------------------------------
282
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200283TF-A BL2 is the bootlader for the SPMC and SPs in the secure world.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200284
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200285SPs may be signed by different parties (SiP, OEM/ODM, TOS vendor, etc.).
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200286Thus they are supplied as distinct signed entities within the FIP flash
287image. The FIP image itself is not signed hence this provides the ability
288to upgrade SPs in the field.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200289
290Booting through TF-A
291--------------------
292
293SP manifests
294~~~~~~~~~~~~
295
296An SP manifest describes SP attributes as defined in `[1]`_
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200297(partition manifest at virtual FF-A instance) in DTS format. It is
298represented as a single file associated with the SP. A sample is
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200299provided by `[5]`_. A binding document is provided by `[6]`_.
300
301Secure Partition packages
302~~~~~~~~~~~~~~~~~~~~~~~~~
303
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200304Secure partitions are bundled as independent package files consisting
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200305of:
306
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200307- a header
308- a DTB
309- an image payload
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200310
311The header starts with a magic value and offset values to SP DTB and
312image payload. Each SP package is loaded independently by BL2 loader
313and verified for authenticity and integrity.
314
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200315The SP package identified by its UUID (matching FF-A uuid property) is
316inserted as a single entry into the FIP at end of the TF-A build flow
317as shown:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200318
319.. code:: shell
320
321 Trusted Boot Firmware BL2: offset=0x1F0, size=0x8AE1, cmdline="--tb-fw"
322 EL3 Runtime Firmware BL31: offset=0x8CD1, size=0x13000, cmdline="--soc-fw"
323 Secure Payload BL32 (Trusted OS): offset=0x1BCD1, size=0x15270, cmdline="--tos-fw"
324 Non-Trusted Firmware BL33: offset=0x30F41, size=0x92E0, cmdline="--nt-fw"
325 HW_CONFIG: offset=0x3A221, size=0x2348, cmdline="--hw-config"
326 TB_FW_CONFIG: offset=0x3C569, size=0x37A, cmdline="--tb-fw-config"
327 SOC_FW_CONFIG: offset=0x3C8E3, size=0x48, cmdline="--soc-fw-config"
328 TOS_FW_CONFIG: offset=0x3C92B, size=0x427, cmdline="--tos-fw-config"
329 NT_FW_CONFIG: offset=0x3CD52, size=0x48, cmdline="--nt-fw-config"
330 B4B5671E-4A90-4FE1-B81F-FB13DAE1DACB: offset=0x3CD9A, size=0xC168, cmdline="--blob"
331 D1582309-F023-47B9-827C-4464F5578FC8: offset=0x48F02, size=0xC168, cmdline="--blob"
332
333.. uml:: ../resources/diagrams/plantuml/fip-secure-partitions.puml
334
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200335Describing secure partitions
336~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200337
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200338A json-formatted description file is passed to the build flow specifying paths
339to the SP binary image and associated DTS partition manifest file. The latter
340is processed by the dtc compiler to generate a DTB fed into the SP package.
341This file also specifies the SP owner (as an optional field) identifying the
342signing domain in case of dual root CoT.
343The SP owner can either be the silicon or the platform provider. The
344corresponding "owner" field value can either take the value of "SiP" or "Plat".
345In absence of "owner" field, it defaults to "SiP" owner.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200346
347.. code:: shell
348
349 {
350 "tee1" : {
351 "image": "tee1.bin",
Manish Pandey77870962020-08-12 17:06:25 +0100352 "pm": "tee1.dts",
353 "owner": "SiP"
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200354 },
355
356 "tee2" : {
357 "image": "tee2.bin",
Manish Pandey77870962020-08-12 17:06:25 +0100358 "pm": "tee2.dts",
359 "owner": "Plat"
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200360 }
361 }
362
363SPMC manifest
364~~~~~~~~~~~~~
365
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200366This manifest contains the SPMC *attribute* node consumed by the SPMD at boot
367time. It implements `[1]`_ (SP manifest at physical FF-A instance) and serves
368two different cases:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200369
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200370- The SPMC resides at S-EL1: the SPMC manifest is used by the SPMD to setup a
371 SP that co-resides with the SPMC and executes at S-EL1 or Secure Supervisor
372 mode.
373- The SPMC resides at S-EL2: the SPMC manifest is used by the SPMD to setup
374 the environment required by the SPMC to run at S-EL2. SPs run at S-EL1 or
375 S-EL0.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200376
377.. code:: shell
378
379 attribute {
380 spmc_id = <0x8000>;
381 maj_ver = <0x1>;
382 min_ver = <0x0>;
383 exec_state = <0x0>;
384 load_address = <0x0 0x6000000>;
385 entrypoint = <0x0 0x6000000>;
386 binary_size = <0x60000>;
387 };
388
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200389- *spmc_id* defines the endpoint ID value that SPMC can query through
390 ``FFA_ID_GET``.
391- *maj_ver/min_ver*. SPMD checks provided version versus its internal
392 version and aborts if not matching.
393- *exec_state* defines the SPMC execution state (AArch64 or AArch32).
394 Notice Hafnium used as a SPMC only supports AArch64.
395- *load_address* and *binary_size* are mostly used to verify secondary
396 entry points fit into the loaded binary image.
397- *entrypoint* defines the cold boot primary core entry point used by
398 SPMD (currently matches ``BL32_BASE``) to enter the SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200399
400Other nodes in the manifest are consumed by Hafnium in the secure world.
401A sample can be found at [7]:
402
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200403- The *hypervisor* node describes SPs. *is_ffa_partition* boolean attribute
404 indicates a FF-A compliant SP. The *load_address* field specifies the load
405 address at which TF-A loaded the SP package.
406- *cpus* node provide the platform topology and allows MPIDR to VMPIDR mapping.
407 Note the primary core is declared first, then secondary core are declared
408 in reverse order.
409- The *memory* node provides platform information on the ranges of memory
410 available to the SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200411
412SPMC boot
413~~~~~~~~~
414
415The SPMC is loaded by BL2 as the BL32 image.
416
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +0200417The SPMC manifest is loaded by BL2 as the ``TOS_FW_CONFIG`` image `[9]`_.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200418
419BL2 passes the SPMC manifest address to BL31 through a register.
420
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200421At boot time, the SPMD in BL31 runs from the primary core, initializes the core
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +0200422contexts and launches the SPMC (BL32) passing the following information through
423registers:
424
425- X0 holds the ``TOS_FW_CONFIG`` physical address (or SPMC manifest blob).
426- X1 holds the ``HW_CONFIG`` physical address.
427- X4 holds the currently running core linear id.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200428
429Loading of SPs
430~~~~~~~~~~~~~~
431
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200432At boot time, BL2 loads SPs sequentially in addition to the SPMC as depicted
433below:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200434
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200435.. uml:: ../resources/diagrams/plantuml/bl2-loading-sp.puml
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200436
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200437Note this boot flow is an implementation sample on Arm's FVP platform.
438Platforms not using TF-A's *Firmware CONFiguration* framework would adjust to a
439different implementation.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200440
441Secure boot
442~~~~~~~~~~~
443
444The SP content certificate is inserted as a separate FIP item so that BL2 loads SPMC,
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200445SPMC manifest, secure partitions and verifies them for authenticity and integrity.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200446Refer to TBBR specification `[3]`_.
447
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200448The multiple-signing domain feature (in current state dual signing domain `[8]`_) allows
449the use of two root keys namely S-ROTPK and NS-ROTPK:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200450
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200451- SPMC (BL32) and SPMC manifest are signed by the SiP using the S-ROTPK.
452- BL33 may be signed by the OEM using NS-ROTPK.
453- An SP may be signed either by SiP (using S-ROTPK) or by OEM (using NS-ROTPK).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200454
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200455Also refer to `Describing secure partitions`_ and `TF-A build options`_ sections.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200456
457Hafnium in the secure world
458===========================
459
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200460General considerations
461----------------------
462
463Build platform for the secure world
464~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
465
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200466In the Hafnium reference implementation specific code parts are only relevant to
467the secure world. Such portions are isolated in architecture specific files
468and/or enclosed by a ``SECURE_WORLD`` macro.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200469
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200470Secure partitions CPU scheduling
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200471~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
472
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200473The FF-A v1.0 specification `[1]`_ provides two ways to relinquinsh CPU time to
474secure partitions. For this a VM (Hypervisor or OS kernel), or SP invokes one of:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200475
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200476- the FFA_MSG_SEND_DIRECT_REQ interface.
477- the FFA_RUN interface.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200478
479Platform topology
480~~~~~~~~~~~~~~~~~
481
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200482The *execution-ctx-count* SP manifest field can take the value of one or the
483total number of PEs. The FF-A v1.0 specification `[1]`_ recommends the
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200484following SP types:
485
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200486- Pinned MP SPs: an execution context matches a physical PE. MP SPs must
487 implement the same number of ECs as the number of PEs in the platform.
488- Migratable UP SPs: a single execution context can run and be migrated on any
489 physical PE. Such SP declares a single EC in its SP manifest. An UP SP can
490 receive a direct message request originating from any physical core targeting
491 the single execution context.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200492
493Parsing SP partition manifests
494------------------------------
495
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200496Hafnium consumes SP manifests as defined in `[1]`_ and `SP manifests`_.
497Note the current implementation may not implement all optional fields.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200498
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200499The SP manifest may contain memory and device regions nodes. In case of
500an S-EL2 SPMC:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200501
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200502- Memory regions are mapped in the SP EL1&0 Stage-2 translation regime at
503 load time (or EL1&0 Stage-1 for an S-EL1 SPMC). A memory region node can
504 specify RX/TX buffer regions in which case it is not necessary for an SP
505 to explicitly invoke the ``FFA_RXTX_MAP`` interface.
506- Device regions are mapped in the SP EL1&0 Stage-2 translation regime (or
507 EL1&0 Stage-1 for an S-EL1 SPMC) as peripherals and possibly allocate
508 additional resources (e.g. interrupts).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200509
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200510For the S-EL2 SPMC, base addresses for memory and device region nodes are IPAs
511provided the SPMC identity maps IPAs to PAs within SP EL1&0 Stage-2 translation
512regime.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200513
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200514Note: in the current implementation both VTTBR_EL2 and VSTTBR_EL2 point to the
515same set of page tables. It is still open whether two sets of page tables shall
516be provided per SP. The memory region node as defined in the specification
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200517provides a memory security attribute hinting to map either to the secure or
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200518non-secure EL1&0 Stage-2 table if it exists.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200519
520Passing boot data to the SP
521---------------------------
522
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200523In `[1]`_ , the "Protocol for passing data" section defines a method for passing
524boot data to SPs (not currently implemented).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200525
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200526Provided that the whole secure partition package image (see
527`Secure Partition packages`_) is mapped to the SP secure EL1&0 Stage-2
528translation regime, an SP can access its own manifest DTB blob and extract its
529partition manifest properties.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200530
531SP Boot order
532-------------
533
534SP manifests provide an optional boot order attribute meant to resolve
535dependencies such as an SP providing a service required to properly boot
J-Alves855fc882021-12-14 16:02:27 +0000536another SP. SPMC boots the SPs in accordance to the boot order attribute,
537lowest to the highest value. If the boot order attribute is absent from the FF-A
538manifest, the SP is treated as if it had the highest boot order value
539(i.e. lowest booting priority).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200540
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200541It is possible for an SP to call into another SP through a direct request
542provided the latter SP has already been booted.
543
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200544Boot phases
545-----------
546
547Primary core boot-up
548~~~~~~~~~~~~~~~~~~~~
549
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200550Upon boot-up, BL31 hands over to the SPMC (BL32) on the primary boot physical
551core. The SPMC performs its platform initializations and registers the SPMC
552secondary physical core entry point physical address by the use of the
J-Alvesc9ca31c2021-10-04 14:33:51 +0100553`FFA_SECONDARY_EP_REGISTER`_ interface (SMC invocation from the SPMC to the SPMD
554at secure physical FF-A instance).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200555
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200556The SPMC then creates secure partitions based on SP packages and manifests. Each
557secure partition is launched in sequence (`SP Boot order`_) on their "primary"
558execution context. If the primary boot physical core linear id is N, an MP SP is
559started using EC[N] on PE[N] (see `Platform topology`_). If the partition is a
560UP SP, it is started using its unique EC0 on PE[N].
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200561
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200562The SP primary EC (or the EC used when the partition is booted as described
563above):
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200564
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200565- Performs the overall SP boot time initialization, and in case of a MP SP,
566 prepares the SP environment for other execution contexts.
567- In the case of a MP SP, it invokes the FFA_SECONDARY_EP_REGISTER at secure
568 virtual FF-A instance (SMC invocation from SP to SPMC) to provide the IPA
569 entry point for other execution contexts.
570- Exits through ``FFA_MSG_WAIT`` to indicate successful initialization or
571 ``FFA_ERROR`` in case of failure.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200572
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200573Secondary cores boot-up
574~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200575
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200576Once the system is started and NWd brought up, a secondary physical core is
577woken up by the ``PSCI_CPU_ON`` service invocation. The TF-A SPD hook mechanism
578calls into the SPMD on the newly woken up physical core. Then the SPMC is
579entered at the secondary physical core entry point.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200580
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200581In the current implementation, the first SP is resumed on the coresponding EC
582(the virtual CPU which matches the physical core). The implication is that the
583first SP must be a MP SP.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200584
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200585In a linux based system, once secure and normal worlds are booted but prior to
586a NWd FF-A driver has been loaded:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200587
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200588- The first SP has initialized all its ECs in response to primary core boot up
589 (at system initialization) and secondary core boot up (as a result of linux
590 invoking PSCI_CPU_ON for all secondary cores).
591- Other SPs have their first execution context initialized as a result of secure
592 world initialization on the primary boot core. Other ECs for those SPs have to
593 be run first through ffa_run to complete their initialization (which results
594 in the EC completing with FFA_MSG_WAIT).
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200595
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200596Refer to `Power management`_ for further details.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200597
J-Alvesc9ca31c2021-10-04 14:33:51 +0100598Notifications
599-------------
600
601The FF-A v1.1 specification `[1]`_ defines notifications as an asynchronous
602communication mechanism with non-blocking semantics. It allows for one FF-A
603endpoint to signal another for service provision, without hindering its current
604progress.
605
606Hafnium currently supports 64 notifications. The IDs of each notification define
607a position in a 64-bit bitmap.
608
609The signaling of notifications can interchangeably happen between NWd and SWd
610FF-A endpoints.
611
612The SPMC is in charge of managing notifications from SPs to SPs, from SPs to
613VMs, and from VMs to SPs. An hypervisor component would only manage
614notifications from VMs to VMs. Given the SPMC has no visibility of the endpoints
615deployed in NWd, the Hypervisor or OS kernel must invoke the interface
616FFA_NOTIFICATION_BITMAP_CREATE to allocate the notifications bitmap per FF-A
617endpoint in the NWd that supports it.
618
619A sender can signal notifications once the receiver has provided it with
620permissions. Permissions are provided by invoking the interface
621FFA_NOTIFICATION_BIND.
622
623Notifications are signaled by invoking FFA_NOTIFICATION_SET. Henceforth
624they are considered to be in a pending sate. The receiver can retrieve its
625pending notifications invoking FFA_NOTIFICATION_GET, which, from that moment,
626are considered to be handled.
627
628Per the FF-A v1.1 spec, each FF-A endpoint must be associated with a scheduler
629that is in charge of donating CPU cycles for notifications handling. The
630FF-A driver calls FFA_NOTIFICATION_INFO_GET to retrieve the information about
631which FF-A endpoints have pending notifications. The receiver scheduler is
632called and informed by the FF-A driver, and it should allocate CPU cycles to the
633receiver.
634
635There are two types of notifications supported:
636- Global, which are targeted to a FF-A endpoint and can be handled within any of
637its execution contexts, as determined by the scheduler of the system.
638- Per-vCPU, which are targeted to a FF-A endpoint and to be handled within a
639a specific execution context, as determined by the sender.
640
641The type of a notification is set when invoking FFA_NOTIFICATION_BIND to give
642permissions to the sender.
643
644Notification signaling resorts to two interrupts:
645- Schedule Receiver Interrupt: Non-secure physical interrupt to be handled by
646the FF-A 'transport' driver within the receiver scheduler. At initialization
647the SPMC (as suggested by the spec) configures a secure SGI, as non-secure, and
648triggers it when there are pending notifications, and the respective receivers
649need CPU cycles to handle them.
650- Notifications Pending Interrupt: Virtual Interrupt to be handled by the
651receiver of the notification. Set when there are pending notifications. For
652per-vCPU the NPI is pended at the handling of FFA_NOTIFICATION_SET interface.
653
654The notifications receipt support is enabled in the partition FF-A manifest.
655
656The subsequent section provides more details about the each one of the
657FF-A interfaces for notifications support.
658
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200659Mandatory interfaces
660--------------------
661
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200662The following interfaces are exposed to SPs:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200663
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200664- ``FFA_VERSION``
665- ``FFA_FEATURES``
666- ``FFA_RX_RELEASE``
667- ``FFA_RXTX_MAP``
J-Alvesc9ca31c2021-10-04 14:33:51 +0100668- ``FFA_RXTX_UNMAP``
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200669- ``FFA_PARTITION_INFO_GET``
670- ``FFA_ID_GET``
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200671- ``FFA_MSG_WAIT``
672- ``FFA_MSG_SEND_DIRECT_REQ``
673- ``FFA_MSG_SEND_DIRECT_RESP``
674- ``FFA_MEM_DONATE``
675- ``FFA_MEM_LEND``
676- ``FFA_MEM_SHARE``
677- ``FFA_MEM_RETRIEVE_REQ``
678- ``FFA_MEM_RETRIEVE_RESP``
679- ``FFA_MEM_RELINQUISH``
680- ``FFA_MEM_RECLAIM``
J-Alvesc9ca31c2021-10-04 14:33:51 +0100681
682As part of the support of FF-A v1.1, the following interfaces were added:
683
684 - ``FFA_NOTIFICATION_BITMAP_CREATE``
685 - ``FFA_NOTIFICATION_BITMAP_DESTROY``
686 - ``FFA_NOTIFICATION_BIND``
687 - ``FFA_NOTIFICATION_UNBIND``
688 - ``FFA_NOTIFICATION_SET``
689 - ``FFA_NOTIFICATION_GET``
690 - ``FFA_NOTIFICATION_INFO_GET``
691 - ``FFA_SPM_ID_GET``
692 - ``FFA_SECONDARY_EP_REGISTER``
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200693
694FFA_VERSION
695~~~~~~~~~~~
696
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200697``FFA_VERSION`` requires a *requested_version* parameter from the caller.
698The returned value depends on the caller:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200699
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200700- Hypervisor or OS kernel in NS-EL1/EL2: the SPMD returns the SPMC version
701 specified in the SPMC manifest.
702- SP: the SPMC returns its own implemented version.
703- SPMC at S-EL1/S-EL2: the SPMD returns its own implemented version.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200704
705FFA_FEATURES
706~~~~~~~~~~~~
707
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200708FF-A features supported by the SPMC may be discovered by secure partitions at
709boot (that is prior to NWd is booted) or run-time.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200710
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200711The SPMC calling FFA_FEATURES at secure physical FF-A instance always get
712FFA_SUCCESS from the SPMD.
713
714The request made by an Hypervisor or OS kernel is forwarded to the SPMC and
715the response relayed back to the NWd.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200716
717FFA_RXTX_MAP/FFA_RXTX_UNMAP
718~~~~~~~~~~~~~~~~~~~~~~~~~~~
719
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200720When invoked from a secure partition FFA_RXTX_MAP maps the provided send and
721receive buffers described by their IPAs to the SP EL1&0 Stage-2 translation
722regime as secure buffers in the MMU descriptors.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200723
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200724When invoked from the Hypervisor or OS kernel, the buffers are mapped into the
725SPMC EL2 Stage-1 translation regime and marked as NS buffers in the MMU
726descriptors.
727
J-Alvesc9ca31c2021-10-04 14:33:51 +0100728The FFA_RXTX_UNMAP unmaps the RX/TX pair from the translation regime of the
729caller, either it being the Hypervisor or OS kernel, as well as a secure
730partition.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200731
732FFA_PARTITION_INFO_GET
733~~~~~~~~~~~~~~~~~~~~~~
734
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200735Partition info get call can originate:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200736
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200737- from SP to SPMC
738- from Hypervisor or OS kernel to SPMC. The request is relayed by the SPMD.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200739
740FFA_ID_GET
741~~~~~~~~~~
742
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200743The FF-A id space is split into a non-secure space and secure space:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200744
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200745- FF-A ID with bit 15 clear relates to VMs.
746- FF-A ID with bit 15 set related to SPs.
747- FF-A IDs 0, 0xffff, 0x8000 are assigned respectively to the Hypervisor, SPMD
748 and SPMC.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200749
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200750The SPMD returns:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200751
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200752- The default zero value on invocation from the Hypervisor.
753- The ``spmc_id`` value specified in the SPMC manifest on invocation from
754 the SPMC (see `SPMC manifest`_)
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200755
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200756This convention helps the SPMC to determine the origin and destination worlds in
757an FF-A ABI invocation. In particular the SPMC shall filter unauthorized
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200758transactions in its world switch routine. It must not be permitted for a VM to
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200759use a secure FF-A ID as origin world by spoofing:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200760
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200761- A VM-to-SP direct request/response shall set the origin world to be non-secure
762 (FF-A ID bit 15 clear) and destination world to be secure (FF-A ID bit 15
763 set).
764- Similarly, an SP-to-SP direct request/response shall set the FF-A ID bit 15
765 for both origin and destination IDs.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200766
767An incoming direct message request arriving at SPMD from NWd is forwarded to
768SPMC without a specific check. The SPMC is resumed through eret and "knows" the
769message is coming from normal world in this specific code path. Thus the origin
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200770endpoint ID must be checked by SPMC for being a normal world ID.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200771
772An SP sending a direct message request must have bit 15 set in its origin
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200773endpoint ID and this can be checked by the SPMC when the SP invokes the ABI.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200774
775The SPMC shall reject the direct message if the claimed world in origin endpoint
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200776ID is not consistent:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200777
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200778- It is either forwarded by SPMD and thus origin endpoint ID must be a "normal
779 world ID",
780- or initiated by an SP and thus origin endpoint ID must be a "secure world ID".
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200781
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200782
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200783FFA_MSG_SEND_DIRECT_REQ/FFA_MSG_SEND_DIRECT_RESP
784~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200785
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200786This is a mandatory interface for secure partitions consisting in direct request
787and responses with the following rules:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200788
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200789- An SP can send a direct request to another SP.
790- An SP can receive a direct request from another SP.
791- An SP can send a direct response to another SP.
792- An SP cannot send a direct request to an Hypervisor or OS kernel.
793- An Hypervisor or OS kernel can send a direct request to an SP.
794- An SP can send a direct response to an Hypervisor or OS kernel.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200795
J-Alvesc9ca31c2021-10-04 14:33:51 +0100796FFA_NOTIFICATION_BITMAP_CREATE/FFA_NOTIFICATION_BITMAP_DESTROY
797~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
798
799The secure partitions notifications bitmap are statically allocated by the SPMC.
800Hence, this interface is not to be issued by secure partitions.
801
802At initialization, the SPMC is not aware of VMs/partitions deployed in the
803normal world. Hence, the Hypervisor or OS kernel must use both ABIs for SPMC
804to be prepared to handle notifications for the provided VM ID.
805
806FFA_NOTIFICATION_BIND/FFA_NOTIFICATION_UNBIND
807~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
808
809Pair of interfaces to manage permissions to signal notifications. Prior to
810handling notifications, an FF-A endpoint must allow a given sender to signal a
811bitmap of notifications.
812
813If the receiver doesn't have notification support enabled in its FF-A manifest,
814it won't be able to bind notifications, hence forbidding it to receive any
815notifications.
816
817FFA_NOTIFICATION_SET/FFA_NOTIFICATION_GET
818~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
819
820If the notifications set are per-vCPU, the NPI interrupt is set as pending
821for a given receiver partition.
822
823The FFA_NOTIFICATION_GET will retrieve all pending global notifications and all
824pending per-vCPU notifications targeted to the current vCPU.
825
826Hafnium keeps the global counting of the pending notifications, which is
827incremented and decremented at the handling of FFA_NOTIFICATION_SET and
828FFA_NOTIFICATION_GET, respectively. If the counter reaches zero, prior to SPMC
829triggering the SRI, it won't be triggered.
830
831FFA_NOTIFICATION_INFO_GET
832~~~~~~~~~~~~~~~~~~~~~~~~~
833
834Hafnium keeps the global counting of pending notifications whose info has been
835retrieved by this interface. The counting is incremented and decremented at the
836handling of FFA_NOTIFICATION_INFO_GET and FFA_NOTIFICATION_GET, respectively.
837It also tracks the notifications whose info has been retrieved individually,
838such that it avoids duplicating returned information for subsequent calls to
839FFA_NOTIFICATION_INFO_GET. For each notification, this state information is
840reset when receiver called FFA_NOTIFICATION_GET to retrieve them.
841
842FFA_SPM_ID_GET
843~~~~~~~~~~~~~~
844
845Returns the FF-A ID allocated to the SPM component (which includes SPMC + SPMD).
846At initialization, the SPMC queries the SPMD for the SPM ID, using this
847same interface, and saves it.
848
849The call emitted at NS and secure physical FF-A instances returns the SPM ID
850specified in the SPMC manifest.
851
852Secure partitions call this interface at the virtual instance, to which the SPMC
853shall return the priorly retrieved SPM ID.
854
855The Hypervisor or OS kernel can issue an FFA_SPM_ID_GET call handled by the
856SPMD, which returns the SPM ID.
857
858FFA_SECONDARY_EP_REGISTER
859~~~~~~~~~~~~~~~~~~~~~~~~~
860
861When the SPMC boots, all secure partitions are initialized on their primary
862Execution Context.
863
864The interface FFA_SECONDARY_EP_REGISTER is to be used by a secure partitions
865from its first execution context, to provide the entry point address for
866secondary execution contexts.
867
868A secondary EC is first resumed either upon invocation of PSCI_CPU_ON from
869the NWd or by invocation of FFA_RUN.
870
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200871SPMC-SPMD direct requests/responses
872-----------------------------------
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200873
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200874Implementation-defined FF-A IDs are allocated to the SPMC and SPMD.
875Using those IDs in source/destination fields of a direct request/response
876permits SPMD to SPMC communication and either way.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200877
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200878- SPMC to SPMD direct request/response uses SMC conduit.
879- SPMD to SPMC direct request/response uses ERET conduit.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200880
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200881PE MMU configuration
882--------------------
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200883
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200884With secure virtualization enabled, two IPA spaces are output from the secure
885EL1&0 Stage-1 translation (secure and non-secure). The EL1&0 Stage-2 translation
886hardware is fed by:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200887
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200888- A single secure IPA space when the SP EL1&0 Stage-1 MMU is disabled.
889- Two IPA spaces (secure and non-secure) when the SP EL1&0 Stage-1 MMU is
890 enabled.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200891
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200892``VTCR_EL2`` and ``VSTCR_EL2`` provide configuration bits for controlling the
893NS/S IPA translations.
894``VSTCR_EL2.SW`` = 0, ``VSTCR_EL2.SA`` = 0,``VTCR_EL2.NSW`` = 0, ``VTCR_EL2.NSA`` = 1:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200895
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200896- Stage-2 translations for the NS IPA space access the NS PA space.
897- Stage-2 translation table walks for the NS IPA space are to the secure PA space.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200898
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200899Secure and non-secure IPA regions use the same set of Stage-2 page tables within
900a SP.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200901
902Interrupt management
903--------------------
904
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200905GIC ownership
906~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200907
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200908The SPMC owns the GIC configuration. Secure and non-secure interrupts are
909trapped at S-EL2. The SPMC manages interrupt resources and allocates interrupt
910IDs based on SP manifests. The SPMC acknowledges physical interrupts and injects
911virtual interrupts by setting the use of vIRQ/vFIQ bits before resuming a SP.
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200912
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200913Non-secure interrupt handling
914~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200915
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200916The following illustrate the scenarios of non secure physical interrupts trapped
917by the SPMC:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200918
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200919- The SP handles a managed exit operation:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200920
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200921.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-managed-exit.png
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200922
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200923- The SP is pre-empted without managed exit:
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200924
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200925.. image:: ../resources/diagrams/ffa-ns-interrupt-handling-sp-preemption.png
Olivier Deprezecb2fe52020-04-02 15:38:02 +0200926
Olivier Deprez5e0a73f2021-04-30 14:42:24 +0200927Secure interrupt handling
Madhukar Pappireddyb3d37b12021-09-23 14:29:05 -0500928-------------------------
929
930This section documents the support implemented for secure interrupt handling in
931SPMC as per the guidance provided by FF-A v1.1 Beta0 specification.
932The following assumptions are made about the system configuration:
933
934 - In the current implementation, S-EL1 SPs are expected to use the para
935 virtualized ABIs for interrupt management rather than accessing virtual GIC
936 interface.
937 - Unless explicitly stated otherwise, this support is applicable only for
938 S-EL1 SPs managed by SPMC.
939 - Secure interrupts are configured as G1S or G0 interrupts.
940 - All physical interrupts are routed to SPMC when running a secure partition
941 execution context.
942
943A physical secure interrupt could preempt normal world execution. Moreover, when
944the execution is in secure world, it is highly likely that the target of a
945secure interrupt is not the currently running execution context of an SP. It
946could be targeted to another FF-A component. Consequently, secure interrupt
947management depends on the state of the target execution context of the SP that
948is responsible for handling the interrupt. Hence, the spec provides guidance on
949how to signal start and completion of secure interrupt handling as discussed in
950further sections.
951
952Secure interrupt signaling mechanisms
953~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
954
955Signaling refers to the mechanisms used by SPMC to indicate to the SP execution
956context that it has a pending virtual interrupt and to further run the SP
957execution context, such that it can handle the virtual interrupt. SPMC uses
958either the FFA_INTERRUPT interface with ERET conduit or vIRQ signal for signaling
959to S-EL1 SPs. When normal world execution is preempted by a secure interrupt,
960the SPMD uses the FFA_INTERRUPT ABI with ERET conduit to signal interrupt to SPMC
961running in S-EL2.
962
963+-----------+---------+---------------+---------------------------------------+
964| SP State | Conduit | Interface and | Description |
965| | | parameters | |
966+-----------+---------+---------------+---------------------------------------+
967| WAITING | ERET, | FFA_INTERRUPT,| SPMC signals to SP the ID of pending |
968| | vIRQ | Interrupt ID | interrupt. It pends vIRQ signal and |
969| | | | resumes execution context of SP |
970| | | | through ERET. |
971+-----------+---------+---------------+---------------------------------------+
972| BLOCKED | ERET, | FFA_INTERRUPT | SPMC signals to SP that an interrupt |
973| | vIRQ | | is pending. It pends vIRQ signal and |
974| | | | resumes execution context of SP |
975| | | | through ERET. |
976+-----------+---------+---------------+---------------------------------------+
977| PREEMPTED | vIRQ | NA | SPMC pends the vIRQ signal but does |
978| | | | not resume execution context of SP. |
979+-----------+---------+---------------+---------------------------------------+
980| RUNNING | ERET, | NA | SPMC pends the vIRQ signal and resumes|
981| | vIRQ | | execution context of SP through ERET. |
982+-----------+---------+---------------+---------------------------------------+
983
984Secure interrupt completion mechanisms
985~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
986
987A SP signals secure interrupt handling completion to the SPMC through the
988following mechanisms:
989
990 - ``FFA_MSG_WAIT`` ABI if it was in WAITING state.
991 - ``FFA_RUN`` ABI if its was in BLOCKED state.
992
993In the current implementation, S-EL1 SPs use para-virtualized HVC interface
994implemented by SPMC to perform priority drop and interrupt deactivation (we
995assume EOImode = 0, i.e. priority drop and deactivation are done together).
996
997If normal world execution was preempted by secure interrupt, SPMC uses
998FFA_NORMAL_WORLD_RESUME ABI to indicate completion of secure interrupt handling
999and further return execution to normal world. If the current SP execution
1000context was preempted by a secure interrupt to be handled by execution context
1001of target SP, SPMC resumes current SP after signal completion by target SP
1002execution context.
1003
1004An action is broadly a set of steps taken by the SPMC in response to a physical
1005interrupt. In order to simplify the design, the current version of secure
1006interrupt management support in SPMC (Hafnium) does not fully implement the
1007Scheduling models and Partition runtime models. However, the current
1008implementation loosely maps to the following actions that are legally allowed
1009by the specification. Please refer to the Table 8.4 in the spec for further
1010description of actions. The action specified for a type of interrupt when the
1011SP is in the message processing running state cannot be less permissive than the
1012action specified for the same type of interrupt when the SP is in the interrupt
1013handling running state.
1014
1015+--------------------+--------------------+------------+-------------+
1016| Runtime Model | NS-Int | Self S-Int | Other S-Int |
1017+--------------------+--------------------+------------+-------------+
1018| Message Processing | Signalable with ME | Signalable | Signalable |
1019+--------------------+--------------------+------------+-------------+
1020| Interrupt Handling | Queued | Queued | Queued |
1021+--------------------+--------------------+------------+-------------+
1022
1023Abbreviations:
1024
1025 - NS-Int: A Non-secure physical interrupt. It requires a switch to the Normal
1026 world to be handled.
1027 - Other S-Int: A secure physical interrupt targeted to an SP different from
1028 the one that is currently running.
1029 - Self S-Int: A secure physical interrupt targeted to the SP that is currently
1030 running.
1031
1032The following figure describes interrupt handling flow when secure interrupt
1033triggers while in normal world:
1034
1035.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-nwd.png
1036
1037A brief description of the events:
1038
1039 - 1) Secure interrupt triggers while normal world is running.
1040 - 2) FIQ gets trapped to EL3.
1041 - 3) SPMD signals secure interrupt to SPMC at S-EL2 using FFA_INTERRUPT ABI.
1042 - 4) SPMC identifies target vCPU of SP and injects virtual interrupt (pends
1043 vIRQ).
1044 - 5) Since SP1 vCPU is in WAITING state, SPMC signals using FFA_INTERRUPT with
1045 interrupt id as argument and resume it using ERET.
1046 - 6) Execution traps to vIRQ handler in SP1 provided that interrupt is not
1047 masked i.e., PSTATE.I = 0
1048 - 7) SP1 services the interrupt and invokes the de-activation HVC call.
1049 - 8) SPMC does internal state management and further de-activates the physical
1050 interrupt and resumes SP vCPU.
1051 - 9) SP performs secure interrupt completion through FFA_MSG_WAIT ABI.
1052 - 10) SPMC returns control to EL3 using FFA_NORMAL_WORLD_RESUME.
1053 - 11) EL3 resumes normal world execution.
1054
1055The following figure describes interrupt handling flow when secure interrupt
1056triggers while in secure world:
1057
1058.. image:: ../resources/diagrams/ffa-secure-interrupt-handling-swd.png
1059
1060A brief description of the events:
1061
1062 - 1) Secure interrupt triggers while SP2 is running and SP1 is blocked.
1063 - 2) Gets trapped to SPMC as IRQ.
1064 - 3) SPMC finds the target vCPU of secure partition responsible for handling
1065 this secure interrupt. In this scenario, it is SP1.
1066 - 4) SPMC pends vIRQ for SP1 and signals through FFA_INTERRUPT interface.
1067 SPMC further resumes SP1 through ERET conduit.
1068 - 5) Execution traps to vIRQ handler in SP1 provided that interrupt is not
1069 masked i.e., PSTATE.I = 0
1070 - 6) SP1 services the secure interrupt and invokes the de-activation HVC call.
1071 - 7) SPMC does internal state management, de-activates the physical interrupt
1072 and resumes SP1 vCPU.
1073 - 8) Assuming SP1 is in BLOCKED state, SP1 performs secure interrupt completion
1074 through FFA_RUN ABI.
1075 - 9) SPMC resumes the pre-empted vCPU of SP2.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001076
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001077
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001078Power management
1079----------------
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001080
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001081In platforms with or without secure virtualization:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001082
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001083- The NWd owns the platform PM policy.
1084- The Hypervisor or OS kernel is the component initiating PSCI service calls.
1085- The EL3 PSCI library is in charge of the PM coordination and control
1086 (eventually writing to platform registers).
1087- While coordinating PM events, the PSCI library calls backs into the Secure
1088 Payload Dispatcher for events the latter has statically registered to.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001089
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001090When using the SPMD as a Secure Payload Dispatcher:
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001091
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001092- A power management event is relayed through the SPD hook to the SPMC.
1093- In the current implementation only cpu on (svc_on_finish) and cpu off
1094 (svc_off) hooks are registered.
1095- The behavior for the cpu on event is described in `Secondary cores boot-up`_.
1096 The SPMC is entered through its secondary physical core entry point.
1097- The cpu off event occurs when the NWd calls PSCI_CPU_OFF. The method by which
1098 the PM event is conveyed to the SPMC is implementation-defined in context of
1099 FF-A v1.0 (`SPMC-SPMD direct requests/responses`_). It consists in a SPMD-to-SPMC
1100 direct request/response conveying the PM event details and SPMC response.
1101 The SPMD performs a synchronous entry into the SPMC. The SPMC is entered and
1102 updates its internal state to reflect the physical core is being turned off.
1103 In the current implementation no SP is resumed as a consequence. This behavior
1104 ensures a minimal support for CPU hotplug e.g. when initiated by the NWd linux
1105 userspace.
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001106
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001107SMMUv3 support in Hafnium
1108=========================
Madhukar Pappireddya9859062021-02-28 14:01:34 -06001109
1110An SMMU is analogous to an MMU in a CPU. It performs address translations for
1111Direct Memory Access (DMA) requests from system I/O devices.
1112The responsibilities of an SMMU include:
1113
1114- Translation: Incoming DMA requests are translated from bus address space to
1115 system physical address space using translation tables compliant to
1116 Armv8/Armv7 VMSA descriptor format.
1117- Protection: An I/O device can be prohibited from read, write access to a
1118 memory region or allowed.
1119- Isolation: Traffic from each individial device can be independently managed.
1120 The devices are differentiated from each other using unique translation
1121 tables.
1122
1123The following diagram illustrates a typical SMMU IP integrated in a SoC with
1124several I/O devices along with Interconnect and Memory system.
1125
1126.. image:: ../resources/diagrams/MMU-600.png
1127
1128SMMU has several versions including SMMUv1, SMMUv2 and SMMUv3. Hafnium provides
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001129support for SMMUv3 driver in both normal and secure world. A brief introduction
Madhukar Pappireddya9859062021-02-28 14:01:34 -06001130of SMMUv3 functionality and the corresponding software support in Hafnium is
1131provided here.
1132
1133SMMUv3 features
1134---------------
1135
1136- SMMUv3 provides Stage1, Stage2 translation as well as nested (Stage1 + Stage2)
1137 translation support. It can either bypass or abort incoming translations as
1138 well.
1139- Traffic (memory transactions) from each upstream I/O peripheral device,
1140 referred to as Stream, can be independently managed using a combination of
1141 several memory based configuration structures. This allows the SMMUv3 to
1142 support a large number of streams with each stream assigned to a unique
1143 translation context.
1144- Support for Armv8.1 VMSA where the SMMU shares the translation tables with
1145 a Processing Element. AArch32(LPAE) and AArch64 translation table format
1146 are supported by SMMUv3.
1147- SMMUv3 offers non-secure stream support with secure stream support being
1148 optional. Logically, SMMUv3 behaves as if there is an indepdendent SMMU
1149 instance for secure and non-secure stream support.
1150- It also supports sub-streams to differentiate traffic from a virtualized
1151 peripheral associated with a VM/SP.
1152- Additionally, SMMUv3.2 provides support for PEs implementing Armv8.4-A
1153 extensions. Consequently, SPM depends on Secure EL2 support in SMMUv3.2
1154 for providing Secure Stage2 translation support to upstream peripheral
1155 devices.
1156
1157SMMUv3 Programming Interfaces
1158-----------------------------
1159
1160SMMUv3 has three software interfaces that are used by the Hafnium driver to
1161configure the behaviour of SMMUv3 and manage the streams.
1162
1163- Memory based data strutures that provide unique translation context for
1164 each stream.
1165- Memory based circular buffers for command queue and event queue.
1166- A large number of SMMU configuration registers that are memory mapped during
1167 boot time by Hafnium driver. Except a few registers, all configuration
1168 registers have independent secure and non-secure versions to configure the
1169 behaviour of SMMUv3 for translation of secure and non-secure streams
1170 respectively.
1171
1172Peripheral device manifest
1173--------------------------
1174
1175Currently, SMMUv3 driver in Hafnium only supports dependent peripheral devices.
1176These devices are dependent on PE endpoint to initiate and receive memory
1177management transactions on their behalf. The acccess to the MMIO regions of
1178any such device is assigned to the endpoint during boot. Moreover, SMMUv3 driver
1179uses the same stage 2 translations for the device as those used by partition
1180manager on behalf of the PE endpoint. This ensures that the peripheral device
1181has the same visibility of the physical address space as the endpoint. The
1182device node of the corresponding partition manifest (refer to `[1]`_ section 3.2
1183) must specify these additional properties for each peripheral device in the
1184system :
1185
1186- smmu-id: This field helps to identify the SMMU instance that this device is
1187 upstream of.
1188- stream-ids: List of stream IDs assigned to this device.
1189
1190.. code:: shell
1191
1192 smmuv3-testengine {
1193 base-address = <0x00000000 0x2bfe0000>;
1194 pages-count = <32>;
1195 attributes = <0x3>;
1196 smmu-id = <0>;
1197 stream-ids = <0x0 0x1>;
1198 interrupts = <0x2 0x3>, <0x4 0x5>;
1199 exclusive-access;
1200 };
1201
1202SMMUv3 driver limitations
1203-------------------------
1204
1205The primary design goal for the Hafnium SMMU driver is to support secure
1206streams.
1207
1208- Currently, the driver only supports Stage2 translations. No support for
1209 Stage1 or nested translations.
1210- Supports only AArch64 translation format.
1211- No support for features such as PCI Express (PASIDs, ATS, PRI), MSI, RAS,
1212 Fault handling, Performance Monitor Extensions, Event Handling, MPAM.
1213- No support for independent peripheral devices.
1214
Raghu Krishnamurthy7f3f7ce2021-10-17 16:48:29 -07001215S-EL0 Partition support
1216=========================
1217The SPMC (Hafnium) has limited capability to run S-EL0 FF-A partitions using
1218FEAT_VHE (mandatory with ARMv8.1 in non-secure state, and in secure world
1219with ARMv8.4 and FEAT_SEL2).
1220
1221S-EL0 partitions are useful for simple partitions that don't require full
1222Trusted OS functionality. It is also useful to reduce jitter and cycle
1223stealing from normal world since they are more lightweight than VMs.
1224
1225S-EL0 partitions are presented, loaded and initialized the same as S-EL1 VMs by
1226the SPMC. They are differentiated primarily by the 'exception-level' property
1227and the 'execution-ctx-count' property in the SP manifest. They are host apps
1228under the single EL2&0 Stage-1 translation regime controlled by the SPMC and
1229call into the SPMC through SVCs as opposed to HVCs and SMCs. These partitions
1230can use FF-A defined services (FFA_MEM_PERM_*) to update or change permissions
1231for memory regions.
1232
1233S-EL0 partitions are required by the FF-A specification to be UP endpoints,
1234capable of migrating, and the SPMC enforces this requirement. The SPMC allows
1235a S-EL0 partition to accept a direct message from secure world and normal world,
1236and generate direct responses to them.
1237
1238Memory sharing between and with S-EL0 partitions is supported.
1239Indirect messaging, Interrupt handling and Notifications are not supported with
1240S-EL0 partitions and is work in progress, planned for future releases.
1241All S-EL0 partitions must use AArch64. AArch32 S-EL0 partitions are not
1242supported.
1243
1244
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001245References
1246==========
1247
1248.. _[1]:
1249
Olivier Deprez2b0be752021-09-01 10:25:21 +02001250[1] `Arm Firmware Framework for Arm A-profile <https://developer.arm.com/docs/den0077/latest>`__
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001251
1252.. _[2]:
1253
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05001254[2] :ref:`Secure Partition Manager using MM interface<Secure Partition Manager (MM)>`
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001255
1256.. _[3]:
1257
1258[3] `Trusted Boot Board Requirements
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001259Client <https://developer.arm.com/documentation/den0006/d/>`__
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001260
1261.. _[4]:
1262
1263[4] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/lib/el3_runtime/aarch64/context.S#n45
1264
1265.. _[5]:
1266
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001267[5] https://git.trustedfirmware.org/TF-A/tf-a-tests.git/tree/spm/cactus/plat/arm/fvp/fdts/cactus.dts
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001268
1269.. _[6]:
1270
Olivier Deprez9938c132021-04-21 11:22:23 +02001271[6] https://trustedfirmware-a.readthedocs.io/en/latest/components/ffa-manifest-binding.html
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001272
1273.. _[7]:
1274
1275[7] https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_spmc_manifest.dts
1276
1277.. _[8]:
1278
Olivier Deprez5e0a73f2021-04-30 14:42:24 +02001279[8] https://lists.trustedfirmware.org/pipermail/tf-a/2020-February/000296.html
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001280
Olivier Deprez4ab7a4a2021-06-21 09:47:13 +02001281.. _[9]:
1282
1283[9] https://trustedfirmware-a.readthedocs.io/en/latest/design/firmware-design.html#dynamic-configuration-during-cold-boot
1284
Olivier Deprezecb2fe52020-04-02 15:38:02 +02001285--------------
1286
Olivier Deprez9938c132021-04-21 11:22:23 +02001287*Copyright (c) 2020-2021, Arm Limited and Contributors. All rights reserved.*