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Yann Gautieree8f5422019-02-14 11:13:25 +01001/*
Yann Gautier8f268c82020-02-26 13:39:44 +01002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yann Gautieree8f5422019-02-14 11:13:25 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautiere3bf9132019-05-07 18:52:17 +02007#include <assert.h>
8
Yann Gautier35dc0772019-05-13 18:34:48 +02009#include <libfdt.h>
10
Yann Gautieree8f5422019-02-14 11:13:25 +010011#include <platform_def.h>
12
Yann Gautier091eab52019-06-04 18:06:34 +020013#include <drivers/st/stm32_iwdg.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010014#include <lib/xlat_tables/xlat_tables_v2.h>
15
Yann Gautier35dc0772019-05-13 18:34:48 +020016/* Internal layout of the 32bit OTP word board_id */
17#define BOARD_ID_BOARD_NB_MASK GENMASK(31, 16)
18#define BOARD_ID_BOARD_NB_SHIFT 16
19#define BOARD_ID_VARIANT_MASK GENMASK(15, 12)
20#define BOARD_ID_VARIANT_SHIFT 12
21#define BOARD_ID_REVISION_MASK GENMASK(11, 8)
22#define BOARD_ID_REVISION_SHIFT 8
23#define BOARD_ID_BOM_MASK GENMASK(3, 0)
24
25#define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \
26 BOARD_ID_BOARD_NB_SHIFT)
27#define BOARD_ID2VAR(_id) (((_id) & BOARD_ID_VARIANT_MASK) >> \
28 BOARD_ID_VARIANT_SHIFT)
29#define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \
30 BOARD_ID_REVISION_SHIFT)
31#define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK)
32
Yann Gautiera2e2a302019-02-14 11:13:39 +010033#define MAP_SRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
34 STM32MP_SYSRAM_SIZE, \
Yann Gautieree8f5422019-02-14 11:13:25 +010035 MT_MEMORY | \
36 MT_RW | \
37 MT_SECURE | \
38 MT_EXECUTE_NEVER)
39
40#define MAP_DEVICE1 MAP_REGION_FLAT(STM32MP1_DEVICE1_BASE, \
41 STM32MP1_DEVICE1_SIZE, \
42 MT_DEVICE | \
43 MT_RW | \
44 MT_SECURE | \
45 MT_EXECUTE_NEVER)
46
47#define MAP_DEVICE2 MAP_REGION_FLAT(STM32MP1_DEVICE2_BASE, \
48 STM32MP1_DEVICE2_SIZE, \
49 MT_DEVICE | \
50 MT_RW | \
51 MT_SECURE | \
52 MT_EXECUTE_NEVER)
53
54#if defined(IMAGE_BL2)
55static const mmap_region_t stm32mp1_mmap[] = {
56 MAP_SRAM,
57 MAP_DEVICE1,
58 MAP_DEVICE2,
59 {0}
60};
61#endif
62#if defined(IMAGE_BL32)
63static const mmap_region_t stm32mp1_mmap[] = {
64 MAP_SRAM,
65 MAP_DEVICE1,
66 MAP_DEVICE2,
67 {0}
68};
69#endif
70
71void configure_mmu(void)
72{
73 mmap_add(stm32mp1_mmap);
74 init_xlat_tables();
75
76 enable_mmu_svc_mon(0);
77}
Yann Gautiere3bf9132019-05-07 18:52:17 +020078
79unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
80{
81 if (bank == GPIO_BANK_Z) {
82 return GPIOZ;
83 }
84
85 assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
86
87 return GPIOA + (bank - GPIO_BANK_A);
88}
Yann Gautier091eab52019-06-04 18:06:34 +020089
Yann Gautierc7374052019-06-04 18:02:37 +020090static int get_part_number(uint32_t *part_nb)
91{
92 uint32_t part_number;
93 uint32_t dev_id;
94
95 if (stm32mp1_dbgmcu_get_chip_dev_id(&dev_id) < 0) {
96 return -1;
97 }
98
99 if (bsec_shadow_read_otp(&part_number, PART_NUMBER_OTP) != BSEC_OK) {
100 ERROR("BSEC: PART_NUMBER_OTP Error\n");
101 return -1;
102 }
103
104 part_number = (part_number & PART_NUMBER_OTP_PART_MASK) >>
105 PART_NUMBER_OTP_PART_SHIFT;
106
107 *part_nb = part_number | (dev_id << 16);
108
109 return 0;
110}
111
112static int get_cpu_package(uint32_t *cpu_package)
113{
114 uint32_t package;
115
116 if (bsec_shadow_read_otp(&package, PACKAGE_OTP) != BSEC_OK) {
117 ERROR("BSEC: PACKAGE_OTP Error\n");
118 return -1;
119 }
120
121 *cpu_package = (package & PACKAGE_OTP_PKG_MASK) >>
122 PACKAGE_OTP_PKG_SHIFT;
123
124 return 0;
125}
126
127void stm32mp_print_cpuinfo(void)
128{
129 const char *cpu_s, *cpu_r, *pkg;
130 uint32_t part_number;
131 uint32_t cpu_package;
132 uint32_t chip_dev_id;
133 int ret;
134
135 /* MPUs Part Numbers */
136 ret = get_part_number(&part_number);
137 if (ret < 0) {
138 WARN("Cannot get part number\n");
139 return;
140 }
141
142 switch (part_number) {
143 case STM32MP157C_PART_NB:
144 cpu_s = "157C";
145 break;
146 case STM32MP157A_PART_NB:
147 cpu_s = "157A";
148 break;
149 case STM32MP153C_PART_NB:
150 cpu_s = "153C";
151 break;
152 case STM32MP153A_PART_NB:
153 cpu_s = "153A";
154 break;
155 case STM32MP151C_PART_NB:
156 cpu_s = "151C";
157 break;
158 case STM32MP151A_PART_NB:
159 cpu_s = "151A";
160 break;
161 default:
162 cpu_s = "????";
163 break;
164 }
165
166 /* Package */
167 ret = get_cpu_package(&cpu_package);
168 if (ret < 0) {
169 WARN("Cannot get CPU package\n");
170 return;
171 }
172
173 switch (cpu_package) {
174 case PKG_AA_LFBGA448:
175 pkg = "AA";
176 break;
177 case PKG_AB_LFBGA354:
178 pkg = "AB";
179 break;
180 case PKG_AC_TFBGA361:
181 pkg = "AC";
182 break;
183 case PKG_AD_TFBGA257:
184 pkg = "AD";
185 break;
186 default:
187 pkg = "??";
188 break;
189 }
190
191 /* REVISION */
192 ret = stm32mp1_dbgmcu_get_chip_version(&chip_dev_id);
193 if (ret < 0) {
194 WARN("Cannot get CPU version\n");
195 return;
196 }
197
198 switch (chip_dev_id) {
199 case STM32MP1_REV_B:
200 cpu_r = "B";
201 break;
202 default:
203 cpu_r = "?";
204 break;
205 }
206
207 NOTICE("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
208}
209
Yann Gautier35dc0772019-05-13 18:34:48 +0200210void stm32mp_print_boardinfo(void)
211{
212 uint32_t board_id;
213 uint32_t board_otp;
214 int bsec_node, bsec_board_id_node;
215 void *fdt;
216 const fdt32_t *cuint;
217
218 if (fdt_get_address(&fdt) == 0) {
219 panic();
220 }
221
222 bsec_node = fdt_node_offset_by_compatible(fdt, -1, DT_BSEC_COMPAT);
223 if (bsec_node < 0) {
224 return;
225 }
226
227 bsec_board_id_node = fdt_subnode_offset(fdt, bsec_node, "board_id");
228 if (bsec_board_id_node <= 0) {
229 return;
230 }
231
232 cuint = fdt_getprop(fdt, bsec_board_id_node, "reg", NULL);
233 if (cuint == NULL) {
234 panic();
235 }
236
237 board_otp = fdt32_to_cpu(*cuint) / sizeof(uint32_t);
238
239 if (bsec_shadow_read_otp(&board_id, board_otp) != BSEC_OK) {
240 ERROR("BSEC: PART_NUMBER_OTP Error\n");
241 return;
242 }
243
244 if (board_id != 0U) {
245 char rev[2];
246
247 rev[0] = BOARD_ID2REV(board_id) - 1 + 'A';
248 rev[1] = '\0';
249 NOTICE("Board: MB%04x Var%d Rev.%s-%02d\n",
250 BOARD_ID2NB(board_id),
251 BOARD_ID2VAR(board_id),
252 rev,
253 BOARD_ID2BOM(board_id));
254 }
255}
256
Yann Gautieraf19ff92019-06-04 18:23:10 +0200257/* Return true when SoC provides a single Cortex-A7 core, and false otherwise */
258bool stm32mp_is_single_core(void)
259{
260 uint32_t part_number;
261 bool ret = false;
262
263 if (get_part_number(&part_number) < 0) {
264 ERROR("Invalid part number, assume single core chip");
265 return true;
266 }
267
268 switch (part_number) {
269 case STM32MP151A_PART_NB:
270 case STM32MP151C_PART_NB:
271 ret = true;
272 break;
273
274 default:
275 break;
276 }
277
278 return ret;
279}
280
Lionel Debieve0e73d732019-09-16 12:17:09 +0200281/* Return true when device is in closed state */
282bool stm32mp_is_closed_device(void)
283{
284 uint32_t value;
285
286 if ((bsec_shadow_register(DATA0_OTP) != BSEC_OK) ||
287 (bsec_read_otp(&value, DATA0_OTP) != BSEC_OK)) {
288 return true;
289 }
290
291 return (value & DATA0_OTP_SECURED) == DATA0_OTP_SECURED;
292}
293
Yann Gautier091eab52019-06-04 18:06:34 +0200294uint32_t stm32_iwdg_get_instance(uintptr_t base)
295{
296 switch (base) {
297 case IWDG1_BASE:
298 return IWDG1_INST;
299 case IWDG2_BASE:
300 return IWDG2_INST;
301 default:
302 panic();
303 }
304}
305
306uint32_t stm32_iwdg_get_otp_config(uint32_t iwdg_inst)
307{
308 uint32_t iwdg_cfg = 0U;
309 uint32_t otp_value;
310
311#if defined(IMAGE_BL2)
312 if (bsec_shadow_register(HW2_OTP) != BSEC_OK) {
313 panic();
314 }
315#endif
316
317 if (bsec_read_otp(&otp_value, HW2_OTP) != BSEC_OK) {
318 panic();
319 }
320
321 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_HW_POS)) != 0U) {
322 iwdg_cfg |= IWDG_HW_ENABLED;
323 }
324
325 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS)) != 0U) {
326 iwdg_cfg |= IWDG_DISABLE_ON_STOP;
327 }
328
329 if ((otp_value & BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS)) != 0U) {
330 iwdg_cfg |= IWDG_DISABLE_ON_STANDBY;
331 }
332
333 return iwdg_cfg;
334}
335
336#if defined(IMAGE_BL2)
337uint32_t stm32_iwdg_shadow_update(uint32_t iwdg_inst, uint32_t flags)
338{
339 uint32_t otp;
340 uint32_t result;
341
342 if (bsec_shadow_read_otp(&otp, HW2_OTP) != BSEC_OK) {
343 panic();
344 }
345
346 if ((flags & IWDG_DISABLE_ON_STOP) != 0U) {
347 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STOP_POS);
348 }
349
350 if ((flags & IWDG_DISABLE_ON_STANDBY) != 0U) {
351 otp |= BIT(iwdg_inst + HW2_OTP_IWDG_FZ_STANDBY_POS);
352 }
353
354 result = bsec_write_otp(otp, HW2_OTP);
355 if (result != BSEC_OK) {
356 return result;
357 }
358
359 /* Sticky lock OTP_IWDG (read and write) */
360 if (!bsec_write_sr_lock(HW2_OTP, 1U) ||
361 !bsec_write_sw_lock(HW2_OTP, 1U)) {
362 return BSEC_LOCK_FAIL;
363 }
364
365 return BSEC_OK;
366}
367#endif
Yann Gautier8f268c82020-02-26 13:39:44 +0100368
369/* Get the non-secure DDR size */
370uint32_t stm32mp_get_ddr_ns_size(void)
371{
372 static uint32_t ddr_ns_size;
373 uint32_t ddr_size;
374
375 if (ddr_ns_size != 0U) {
376 return ddr_ns_size;
377 }
378
379 ddr_size = dt_get_ddr_size();
380 if ((ddr_size <= (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE)) ||
381 (ddr_size > STM32MP_DDR_MAX_SIZE)) {
382 panic();
383 }
384
385 ddr_ns_size = ddr_size - (STM32MP_DDR_S_SIZE + STM32MP_DDR_SHMEM_SIZE);
386
387 return ddr_ns_size;
388}