| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
| Varun Wadekar | 4fe43a3 | 2018-01-02 14:10:18 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
| Varun Wadekar | 4151af9 | 2019-10-04 11:40:56 -0700 | [diff] [blame] | 3 | * Copyright (c) 2015-2020, NVIDIA Corporation. All rights reserved. |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 4 | * |
| dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 8 | #ifndef PLAT_MACROS_S |
| 9 | #define PLAT_MACROS_S |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 10 | |
| Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 11 | #include <drivers/arm/gicv2.h> |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 12 | #include <tegra_def.h> |
| 13 | |
| 14 | .section .rodata.gic_reg_name, "aS" |
| 15 | gicc_regs: |
| 16 | .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", "" |
| 17 | gicd_pend_reg: |
| 18 | .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n" |
| 19 | newline: |
| 20 | .asciz "\n" |
| 21 | spacer: |
| 22 | .asciz ":\t\t0x" |
| 23 | |
| 24 | /* --------------------------------------------- |
| 25 | * The below macro prints out relevant GIC |
| 26 | * registers whenever an unhandled exception is |
| 27 | * taken in BL31. |
| 28 | * --------------------------------------------- |
| 29 | */ |
| Gerald Lejeune | 2c7ed5b | 2015-11-26 15:47:53 +0100 | [diff] [blame] | 30 | .macro plat_crash_print_regs |
| Varun Wadekar | 4151af9 | 2019-10-04 11:40:56 -0700 | [diff] [blame] | 31 | #ifdef TEGRA_GICC_BASE |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 32 | mov_imm x16, TEGRA_GICC_BASE |
| Varun Wadekar | bfc6605 | 2016-08-23 14:01:19 -0700 | [diff] [blame] | 33 | |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 34 | /* gicc base address is now in x16 */ |
| 35 | adr x6, gicc_regs /* Load the gicc reg list to x6 */ |
| 36 | /* Load the gicc regs to gp regs used by str_in_crash_buf_print */ |
| 37 | ldr w8, [x16, #GICC_HPPIR] |
| 38 | ldr w9, [x16, #GICC_AHPPIR] |
| 39 | ldr w10, [x16, #GICC_CTLR] |
| 40 | /* Store to the crash buf and print to cosole */ |
| 41 | bl str_in_crash_buf_print |
| Varun Wadekar | 4151af9 | 2019-10-04 11:40:56 -0700 | [diff] [blame] | 42 | #endif |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 43 | /* Print the GICD_ISPENDR regs */ |
| Varun Wadekar | bfc6605 | 2016-08-23 14:01:19 -0700 | [diff] [blame] | 44 | mov_imm x16, TEGRA_GICD_BASE |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 45 | add x7, x16, #GICD_ISPENDR |
| 46 | adr x4, gicd_pend_reg |
| 47 | bl asm_print_str |
| 48 | 2: |
| 49 | sub x4, x7, x16 |
| 50 | cmp x4, #0x280 |
| 51 | b.eq 1f |
| 52 | bl asm_print_hex |
| 53 | adr x4, spacer |
| 54 | bl asm_print_str |
| Varun Wadekar | 4fe43a3 | 2018-01-02 14:10:18 -0800 | [diff] [blame] | 55 | ldr w4, [x7], #4 |
| Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 56 | bl asm_print_hex |
| 57 | adr x4, newline |
| 58 | bl asm_print_str |
| 59 | b 2b |
| 60 | 1: |
| 61 | .endm |
| 62 | |
| Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 63 | #endif /* PLAT_MACROS_S */ |