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Rex-BC Chen749b2112021-09-28 11:24:09 +08001/*
2 * Copyright (c) 2021, MediaTek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
developerc3dabd82021-11-08 11:30:40 +08007/* common headers */
8#include <assert.h>
9
10#include <arch_helpers.h>
James Lo4ac7a412021-10-06 18:12:30 +080011#include <common/debug.h>
Rex-BC Chen047d85e2021-11-22 18:14:38 +080012#include <drivers/gpio.h>
Rex-BC Chen749b2112021-09-28 11:24:09 +080013#include <lib/psci/psci.h>
14
developerc3dabd82021-11-08 11:30:40 +080015/* platform specific headers */
16#include <mt_gic_v3.h>
17#include <mtspmc.h>
18#include <plat/common/platform.h>
19#include <plat_mtk_lpm.h>
20#include <plat_params.h>
21#include <plat_pm.h>
Rex-BC Chendc0f9f72021-11-22 17:55:56 +080022#include <pmic.h>
23#include <rtc.h>
developerc3dabd82021-11-08 11:30:40 +080024
25/*
26 * Cluster state request:
27 * [0] : The CPU requires cluster power down
28 * [1] : The CPU requires cluster power on
29 */
30#define coordinate_cluster(onoff) write_clusterpwrdn_el1(onoff)
31#define coordinate_cluster_pwron() coordinate_cluster(1)
32#define coordinate_cluster_pwroff() coordinate_cluster(0)
33
34/* platform secure entry point */
35static uintptr_t secure_entrypoint;
36/* per-CPU power state */
37static unsigned int plat_power_state[PLATFORM_CORE_COUNT];
38
39/* platform CPU power domain - ops */
40static const struct mt_lpm_tz *plat_mt_pm;
41
42static inline int plat_mt_pm_invoke(int (*func)(unsigned int cpu,
43 const psci_power_state_t *state),
44 int cpu, const psci_power_state_t *state)
45{
46 int ret = -1;
47
48 if (func != NULL) {
49 ret = func(cpu, state);
50 }
51 return ret;
52}
53
54/*
55 * Common MTK_platform operations to power on/off a
56 * CPU in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
57 */
58static void plat_cpu_pwrdwn_common(unsigned int cpu,
59 const psci_power_state_t *state, unsigned int req_pstate)
60{
61 assert(cpu == plat_my_core_pos());
62 assert(plat_mt_pm != NULL);
63
64 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_dwn, cpu, state);
65
66 if ((psci_get_pstate_pwrlvl(req_pstate) >= MTK_AFFLVL_CLUSTER) ||
67 (req_pstate == 0U)) { /* hotplug off */
68 coordinate_cluster_pwroff();
69 }
70
71 /* Prevent interrupts from spuriously waking up this CPU */
72 mt_gic_rdistif_save();
73 gicv3_cpuif_disable(cpu);
74 gicv3_rdistif_off(cpu);
75}
76
77static void plat_cpu_pwron_common(unsigned int cpu,
78 const psci_power_state_t *state, unsigned int req_pstate)
79{
80 assert(cpu == plat_my_core_pos());
81 assert(plat_mt_pm != NULL);
82
83 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_cpu_on, cpu, state);
84
85 coordinate_cluster_pwron();
86
87 /*
88 * If mcusys does power down before then restore
89 * all CPUs' GIC Redistributors
90 */
91 if (IS_MCUSYS_OFF_STATE(state)) {
92 mt_gic_rdistif_restore_all();
93 } else {
94 gicv3_rdistif_on(cpu);
95 gicv3_cpuif_enable(cpu);
96 mt_gic_rdistif_init();
97 mt_gic_rdistif_restore();
98 }
99}
100
101/*
102 * Common MTK_platform operations to power on/off a
103 * cluster in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
104 */
105static void plat_cluster_pwrdwn_common(unsigned int cpu,
106 const psci_power_state_t *state, unsigned int req_pstate)
107{
108 assert(cpu == plat_my_core_pos());
109 assert(plat_mt_pm != NULL);
110
111 if (plat_mt_pm_invoke(plat_mt_pm->pwr_cluster_dwn, cpu, state) != 0) {
112 coordinate_cluster_pwron();
113
114 /*
115 * TODO:
116 * Return on fail and add a 'return' here before
117 * adding any code following the if-block.
118 */
119 }
120}
121
122static void plat_cluster_pwron_common(unsigned int cpu,
123 const psci_power_state_t *state, unsigned int req_pstate)
124{
125 assert(cpu == plat_my_core_pos());
126 assert(plat_mt_pm != NULL);
127
128 if (plat_mt_pm_invoke(plat_mt_pm->pwr_cluster_on, cpu, state) != 0) {
129 /*
130 * TODO:
131 * return on fail and add a 'return' here before
132 * adding any code following the if-block.
133 */
134 }
135}
136
137/*
138 * Common MTK_platform operations to power on/off a
139 * mcusys in response to a CPU_ON, CPU_OFF or CPU_SUSPEND request.
140 */
141static void plat_mcusys_pwrdwn_common(unsigned int cpu,
142 const psci_power_state_t *state, unsigned int req_pstate)
143{
144 assert(cpu == plat_my_core_pos());
145 assert(plat_mt_pm != NULL);
146
147 if (plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_dwn, cpu, state) != 0) {
148 return; /* return on fail */
149 }
150
151 mt_gic_distif_save();
152 gic_sgi_save_all();
153}
154
155static void plat_mcusys_pwron_common(unsigned int cpu,
156 const psci_power_state_t *state, unsigned int req_pstate)
157{
158 assert(cpu == plat_my_core_pos());
159 assert(plat_mt_pm != NULL);
160
161 if (plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_on, cpu, state) != 0) {
162 /* return on fail */
163 return;
164 }
165
166 mt_gic_init();
167 mt_gic_distif_restore();
168 gic_sgi_restore_all();
169
170 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_mcusys_on_finished, cpu, state);
171}
172
173/* plat_psci_ops implementation */
174static void plat_cpu_standby(plat_local_state_t cpu_state)
175{
176 uint64_t scr;
177
178 scr = read_scr_el3();
179 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
180
181 isb();
182 dsb();
183 wfi();
184
185 write_scr_el3(scr);
186}
187
188static int plat_power_domain_on(u_register_t mpidr)
189{
190 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
191 unsigned int cluster = 0U;
192
193 if (cpu >= PLATFORM_CORE_COUNT) {
194 return PSCI_E_INVALID_PARAMS;
195 }
196
197 if (!spm_get_cluster_powerstate(cluster)) {
198 spm_poweron_cluster(cluster);
199 }
200
201 /* init CPU reset arch as AARCH64 */
202 mcucfg_init_archstate(cluster, cpu, true);
203 mcucfg_set_bootaddr(cluster, cpu, secure_entrypoint);
204 spm_poweron_cpu(cluster, cpu);
205
206 return PSCI_E_SUCCESS;
207}
208
209static void plat_power_domain_on_finish(const psci_power_state_t *state)
210{
211 unsigned long mpidr = read_mpidr_el1();
212 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
213
214 assert(cpu < PLATFORM_CORE_COUNT);
215
216 /* Allow IRQs to wakeup this core in IDLE flow */
217 mcucfg_enable_gic_wakeup(0U, cpu);
218
219 if (IS_CLUSTER_OFF_STATE(state)) {
220 plat_cluster_pwron_common(cpu, state, 0U);
221 }
222
223 plat_cpu_pwron_common(cpu, state, 0U);
224}
225
226static void plat_power_domain_off(const psci_power_state_t *state)
227{
228 unsigned long mpidr = read_mpidr_el1();
229 unsigned int cpu = (unsigned int)plat_core_pos_by_mpidr(mpidr);
230
231 assert(cpu < PLATFORM_CORE_COUNT);
232
233 plat_cpu_pwrdwn_common(cpu, state, 0U);
234 spm_poweroff_cpu(0U, cpu);
235
236 /* prevent unintended IRQs from waking up the hot-unplugged core */
237 mcucfg_disable_gic_wakeup(0U, cpu);
238
239 if (IS_CLUSTER_OFF_STATE(state)) {
240 plat_cluster_pwrdwn_common(cpu, state, 0U);
241 }
242}
243
244static void plat_power_domain_suspend(const psci_power_state_t *state)
245{
246 unsigned int cpu = plat_my_core_pos();
247
248 assert(cpu < PLATFORM_CORE_COUNT);
249 assert(plat_mt_pm != NULL);
250
251 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_prompt, cpu, state);
252
253 /* Perform the common CPU specific operations */
254 plat_cpu_pwrdwn_common(cpu, state, plat_power_state[cpu]);
255
256 if (IS_CLUSTER_OFF_STATE(state)) {
257 /* Perform the common cluster specific operations */
258 plat_cluster_pwrdwn_common(cpu, state, plat_power_state[cpu]);
259 }
260
261 if (IS_MCUSYS_OFF_STATE(state)) {
262 /* Perform the common mcusys specific operations */
263 plat_mcusys_pwrdwn_common(cpu, state, plat_power_state[cpu]);
264 }
265}
266
267static void plat_power_domain_suspend_finish(const psci_power_state_t *state)
268{
269 unsigned int cpu = plat_my_core_pos();
270
271 assert(cpu < PLATFORM_CORE_COUNT);
272 assert(plat_mt_pm != NULL);
273
274 if (IS_MCUSYS_OFF_STATE(state)) {
275 /* Perform the common mcusys specific operations */
276 plat_mcusys_pwron_common(cpu, state, plat_power_state[cpu]);
277 }
278
279 if (IS_CLUSTER_OFF_STATE(state)) {
280 /* Perform the common cluster specific operations */
281 plat_cluster_pwron_common(cpu, state, plat_power_state[cpu]);
282 }
283
284 /* Perform the common CPU specific operations */
285 plat_cpu_pwron_common(cpu, state, plat_power_state[cpu]);
286
287 (void)plat_mt_pm_invoke(plat_mt_pm->pwr_reflect, cpu, state);
288}
289
290static int plat_validate_power_state(unsigned int power_state,
291 psci_power_state_t *req_state)
292{
293 unsigned int pstate = psci_get_pstate_type(power_state);
294 unsigned int aff_lvl = psci_get_pstate_pwrlvl(power_state);
295 unsigned int cpu = plat_my_core_pos();
296
297 if (aff_lvl > PLAT_MAX_PWR_LVL) {
298 return PSCI_E_INVALID_PARAMS;
299 }
300
301 if (pstate == PSTATE_TYPE_STANDBY) {
302 req_state->pwr_domain_state[0] = PLAT_MAX_RET_STATE;
303 } else {
304 unsigned int i;
305 unsigned int pstate_id = psci_get_pstate_id(power_state);
306 plat_local_state_t s = MTK_LOCAL_STATE_OFF;
307
308 /* Use pstate_id to be power domain state */
309 if (pstate_id > s) {
310 s = (plat_local_state_t)pstate_id;
311 }
312
313 for (i = 0U; i <= aff_lvl; i++) {
314 req_state->pwr_domain_state[i] = s;
315 }
316 }
317
318 plat_power_state[cpu] = power_state;
319 return PSCI_E_SUCCESS;
320}
321
322static void plat_get_sys_suspend_power_state(psci_power_state_t *req_state)
323{
324 unsigned int lv;
325 unsigned int cpu = plat_my_core_pos();
326
327 for (lv = PSCI_CPU_PWR_LVL; lv <= PLAT_MAX_PWR_LVL; lv++) {
328 req_state->pwr_domain_state[lv] = PLAT_MAX_OFF_STATE;
329 }
330
331 plat_power_state[cpu] =
332 psci_make_powerstate(
333 MT_PLAT_PWR_STATE_SYSTEM_SUSPEND,
334 PSTATE_TYPE_POWERDOWN, PLAT_MAX_PWR_LVL);
335
336 flush_dcache_range((uintptr_t)
337 &plat_power_state[cpu],
338 sizeof(plat_power_state[cpu]));
339}
340
Rex-BC Chen047d85e2021-11-22 18:14:38 +0800341/*******************************************************************************
342 * MTK handlers to shutdown/reboot the system
343 ******************************************************************************/
344static void __dead2 plat_mtk_system_reset(void)
345{
346 struct bl_aux_gpio_info *gpio_reset = plat_get_mtk_gpio_reset();
347
348 INFO("MTK System Reset\n");
349
350 gpio_set_value(gpio_reset->index, gpio_reset->polarity);
351
352 wfi();
353 ERROR("MTK System Reset: operation not handled.\n");
354 panic();
355}
356
Rex-BC Chendc0f9f72021-11-22 17:55:56 +0800357static void __dead2 plat_mtk_system_off(void)
358{
359 INFO("MTK System Off\n");
360
361 rtc_power_off_sequence();
362 pmic_power_off();
363
364 wfi();
365 ERROR("MTK System Off: operation not handled.\n");
366 panic();
367}
368
Rex-BC Chen749b2112021-09-28 11:24:09 +0800369static const plat_psci_ops_t plat_psci_ops = {
developerc3dabd82021-11-08 11:30:40 +0800370 .cpu_standby = plat_cpu_standby,
371 .pwr_domain_on = plat_power_domain_on,
372 .pwr_domain_on_finish = plat_power_domain_on_finish,
373 .pwr_domain_off = plat_power_domain_off,
374 .pwr_domain_suspend = plat_power_domain_suspend,
375 .pwr_domain_suspend_finish = plat_power_domain_suspend_finish,
376 .validate_power_state = plat_validate_power_state,
Rex-BC Chendc0f9f72021-11-22 17:55:56 +0800377 .get_sys_suspend_power_state = plat_get_sys_suspend_power_state,
378 .system_off = plat_mtk_system_off,
Rex-BC Chen047d85e2021-11-22 18:14:38 +0800379 .system_reset = plat_mtk_system_reset,
Rex-BC Chen749b2112021-09-28 11:24:09 +0800380};
381
382int plat_setup_psci_ops(uintptr_t sec_entrypoint,
383 const plat_psci_ops_t **psci_ops)
384{
385 *psci_ops = &plat_psci_ops;
developerc3dabd82021-11-08 11:30:40 +0800386 secure_entrypoint = sec_entrypoint;
387
388 /*
389 * init the warm reset config for boot CPU
390 * reset arch as AARCH64
391 * reset addr as function bl31_warm_entrypoint()
392 */
393 mcucfg_init_archstate(0U, 0U, true);
394 mcucfg_set_bootaddr(0U, 0U, secure_entrypoint);
395
396 spmc_init();
developerba7b7d22021-11-14 10:14:45 +0800397 plat_mt_pm = mt_plat_cpu_pm_init();
Rex-BC Chen749b2112021-09-28 11:24:09 +0800398
399 return 0;
400}