| Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 1 | /* |
| Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 2 | * Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved. |
| Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef PLAT_SOCFPGA_DEF_H |
| 8 | #define PLAT_SOCFPGA_DEF_H |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
| 12 | /* Platform Setting */ |
| Hadi Asyrafi | 786db4d | 2019-12-30 16:00:30 +0800 | [diff] [blame] | 13 | #define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10 |
| 14 | #define BOOT_SOURCE BOOT_SOURCE_SDMMC |
| Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 15 | |
| Sieu Mun Tang | a544da1 | 2022-02-28 15:24:59 +0800 | [diff] [blame] | 16 | /* FPGA config helpers */ |
| 17 | #define INTEL_SIP_SMC_FPGA_CONFIG_ADDR 0x400000 |
| 18 | #define INTEL_SIP_SMC_FPGA_CONFIG_SIZE 0x1000000 |
| 19 | |
| Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 20 | /* Register Mapping */ |
| Abdul Halim, Muhammad Hadi Asyrafi | 616b5e7 | 2020-08-05 22:12:23 +0800 | [diff] [blame] | 21 | #define SOCFPGA_CCU_NOC_REG_BASE 0xf7000000 |
| Sieu Mun Tang | 82cf5df | 2022-05-05 17:07:21 +0800 | [diff] [blame^] | 22 | #define SOCFPGA_F2SDRAMMGR_REG_BASE U(0xf8024000) |
| Abdul Halim, Muhammad Hadi Asyrafi | 616b5e7 | 2020-08-05 22:12:23 +0800 | [diff] [blame] | 23 | |
| Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 24 | #define SOCFPGA_MMC_REG_BASE 0xff808000 |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 25 | |
| Hadi Asyrafi | 67cb0ea | 2019-12-23 13:25:33 +0800 | [diff] [blame] | 26 | #define SOCFPGA_RSTMGR_REG_BASE 0xffd11000 |
| Hadi Asyrafi | 8ebd237 | 2019-12-23 17:58:04 +0800 | [diff] [blame] | 27 | #define SOCFPGA_SYSMGR_REG_BASE 0xffd12000 |
| 28 | |
| 29 | #define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000 |
| 30 | #define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100 |
| 31 | #define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200 |
| 32 | #define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300 |
| 33 | |
| Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 34 | |
| 35 | #endif /* PLATSOCFPGA_DEF_H */ |
| 36 | |