commit 8ebd2375b7267f31c04c95db11fe22fe4d56a555
author Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Mon Dec 23 17:58:04 2019 +0800
committer Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Thu Jan 16 10:53:26 2020 +0800
tree eb3b06310139d4530bde1684497467384ed75999
parent 67cb0eae5d307a4733f0427840cbfbbcb23580e8

intel: System Manager refactoring

Refactored system manager driver to be shared across both intel platform

Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d

plat/intel/soc/stratix10/include/socfpga_plat_def.h

diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 066585e..9dc5151 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -14,7 +14,15 @@
 
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE                    0xff808000
+
 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE		0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE		0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE		0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		0xffd21300
+
 
 #endif /* PLATSOCFPGA_DEF_H */