intel: System Manager refactoring
Refactored system manager driver to be shared across both intel platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d
diff --git a/plat/intel/soc/stratix10/bl2_plat_setup.c b/plat/intel/soc/stratix10/bl2_plat_setup.c
index 2296838..5eb7969 100644
--- a/plat/intel/soc/stratix10/bl2_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl2_plat_setup.c
@@ -20,10 +20,10 @@
#include "socfpga_mailbox.h"
#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
#include "s10_clock_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"
-#include "s10_system_manager.h"
#include "wdt/watchdog.h"
diff --git a/plat/intel/soc/stratix10/bl31_plat_setup.c b/plat/intel/soc/stratix10/bl31_plat_setup.c
index 48dad01..29f57c4 100644
--- a/plat/intel/soc/stratix10/bl31_plat_setup.c
+++ b/plat/intel/soc/stratix10/bl31_plat_setup.c
@@ -18,10 +18,10 @@
#include "socfpga_private.h"
#include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"
#include "s10_clock_manager.h"
-#include "s10_system_manager.h"
static entry_point_info_t bl32_image_ep_info;
diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
deleted file mode 100644
index c34fcf7..0000000
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define S10_FIREWALL_SOC2FPGA 0xffd21200
-#define S10_FIREWALL_LWSOC2FPGA 0xffd21300
-
-/* L3 Interconnect Register Map */
-#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER 0xffd21000
-#define S10_NOC_FW_L4_PER_SCR_NAND_DATA 0xffd21004
-#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER 0xffd2100c
-#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER 0xffd21010
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0 0xffd2101c
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1 0xffd21020
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0 0xffd21024
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1 0xffd21028
-#define S10_NOC_FW_L4_PER_SCR_EMAC0 0xffd2102c
-#define S10_NOC_FW_L4_PER_SCR_EMAC1 0xffd21030
-#define S10_NOC_FW_L4_PER_SCR_EMAC2 0xffd21034
-#define S10_NOC_FW_L4_PER_SCR_SDMMC 0xffd21040
-#define S10_NOC_FW_L4_PER_SCR_GPIO0 0xffd21044
-#define S10_NOC_FW_L4_PER_SCR_GPIO1 0xffd21048
-#define S10_NOC_FW_L4_PER_SCR_I2C0 0xffd21050
-#define S10_NOC_FW_L4_PER_SCR_I2C1 0xffd21054
-#define S10_NOC_FW_L4_PER_SCR_I2C2 0xffd21058
-#define S10_NOC_FW_L4_PER_SCR_I2C3 0xffd2105c
-#define S10_NOC_FW_L4_PER_SCR_I2C4 0xffd21060
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0 0xffd21064
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1 0xffd21068
-#define S10_NOC_FW_L4_PER_SCR_UART0 0xffd2106c
-#define S10_NOC_FW_L4_PER_SCR_UART1 0xffd21070
-
-#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC 0xffd21108
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC 0xffd2110c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC 0xffd21110
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC 0xffd21114
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC 0xffd21118
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC 0xffd2111c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC 0xffd21120
-#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC 0xffd2112c
-#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC 0xffd21130
-#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC 0xffd21134
-#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC 0xffd21138
-#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC 0xffd21140
-#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC 0xffd21144
-#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC 0xffd21148
-#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR 0xffd2114c
-#define S10_NOC_FW_L4_SYS_SCR_IO_MGR 0xffd21154
-#define S10_NOC_FW_L4_SYS_SCR_RST_MGR 0xffd21158
-#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR 0xffd2115c
-#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER 0xffd21160
-#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER 0xffd21164
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0 0xffd21168
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1 0xffd2116c
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2 0xffd21170
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3 0xffd21174
-#define S10_NOC_FW_L4_SYS_SCR_DAP 0xffd21178
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES 0xffd21190
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS 0xffd21194
-
-#define S10_CCU_NOC_CPU0_RAMSPACE0_0 0xf7004688
-#define S10_CCU_NOC_IOM_RAMSPACE0_0 0xf7018628
-
-/* System Manager Register Map */
-#define S10_SYSMGR_CORE(x) (0xffd12000 + (x))
-
-#define SYSMGR_MMC 0x28
-#define SYSMGR_MMC_DRVSEL(x) (((x) & 0x7) << 0)
-
-#define SYSMGR_NOC_TIMEOUT 0xc0
-#define SYSMGR_NOC_IDLEREQ_SET 0xc4
-#define SYSMGR_NOC_IDLEREQ_CLR 0xc8
-#define SYSMGR_NOC_IDLEREQ_VAL 0xcc
-#define SYSMGR_NOC_IDLEACK 0xd0
-#define SYSMGR_NOC_IDLESTATUS 0xd4
-
-#define IDLE_DATA_LWSOC2FPGA BIT(0)
-#define IDLE_DATA_SOC2FPGA BIT(4)
-#define IDLE_DATA_MASK (IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
-
-#define SYSMGR_BOOT_SCRATCH_COLD_0 0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1 0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2 0x208
-
-#define DISABLE_BRIDGE_FIREWALL 0x0ffe0101
-#define DISABLE_L4_FIREWALL (BIT(0) | BIT(16) | BIT(24))
-
-void enable_nonsecure_access(void);
-void enable_ns_peripheral_access(void);
-void enable_ns_bridge_access(void);
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 066585e..9dc5151 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -14,7 +14,15 @@
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000
+
#define SOCFPGA_RSTMGR_REG_BASE 0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE 0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE 0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE 0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE 0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE 0xffd21300
+
#endif /* PLATSOCFPGA_DEF_H */
diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk
index 2b80a94..a89c3d4 100644
--- a/plat/intel/soc/stratix10/platform.mk
+++ b/plat/intel/soc/stratix10/platform.mk
@@ -38,7 +38,6 @@
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
- plat/intel/soc/stratix10/soc/s10_system_manager.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
@@ -46,6 +45,7 @@
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/soc/socfpga_mailbox.c \
plat/intel/soc/common/soc/socfpga_reset_manager.c \
+ plat/intel/soc/common/soc/socfpga_system_manager.c \
plat/intel/soc/common/drivers/qspi/cadence_qspi.c \
plat/intel/soc/common/drivers/wdt/watchdog.c
diff --git a/plat/intel/soc/stratix10/soc/s10_clock_manager.c b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
index e4ff7ac..1e092de 100644
--- a/plat/intel/soc/stratix10/soc/s10_clock_manager.c
+++ b/plat/intel/soc/stratix10/soc/s10_clock_manager.c
@@ -12,8 +12,8 @@
#include <platform_def.h>
#include "s10_clock_manager.h"
-#include "s10_system_manager.h"
#include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
void wait_pll_lock(void)
@@ -190,9 +190,9 @@
ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
/* Pass clock source frequency into scratch register */
- mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1),
hoff_ptr->hps_osc_clk_h);
- mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+ mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2),
hoff_ptr->fpga_clk_hz);
}
@@ -205,14 +205,14 @@
switch (ALT_CLKMGR_PSRC(pllglob)) {
case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1:
- scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
ref_clk = mmio_read_32(scr_reg);
break;
case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC:
ref_clk = ALT_CLKMGR_INTOSC_HZ;
break;
case ALT_CLKMGR_PLLGLOB_PSRC_F2S:
- scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+ scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
ref_clk = mmio_read_32(scr_reg);
break;
default:
diff --git a/plat/intel/soc/stratix10/soc/s10_system_manager.c b/plat/intel/soc/stratix10/soc/s10_system_manager.c
deleted file mode 100644
index 6963e7d..0000000
--- a/plat/intel/soc/stratix10/soc/s10_system_manager.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-#include "s10_system_manager.h"
-
-void enable_nonsecure_access(void)
-{
- enable_ns_peripheral_access();
- enable_ns_bridge_access();
-}
-
-void enable_ns_peripheral_access(void)
-{
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
- DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
-
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
-
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
-
- mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
-
- mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
- mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
-
- mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
-
-}
-
-void enable_ns_bridge_access(void)
-{
- mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
- mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
-}