Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <string.h> |
| 10 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 11 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 16 | #include <smmu.h> |
Varun Wadekar | 82b0b18 | 2019-09-26 08:26:41 -0700 | [diff] [blame^] | 17 | #include <tegra_platform.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 18 | #include <tegra_private.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 19 | |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 20 | extern void memcpy16(void *dest, const void *src, unsigned int length); |
| 21 | |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 22 | #define SMMU_NUM_CONTEXTS 64U |
| 23 | #define SMMU_CONTEXT_BANK_MAX_IDX 64U |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 24 | |
Varun Wadekar | 82b0b18 | 2019-09-26 08:26:41 -0700 | [diff] [blame^] | 25 | #define MISMATCH_DETECTED 0x55AA55AAU |
| 26 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 27 | /* |
| 28 | * Init SMMU during boot or "System Suspend" exit |
| 29 | */ |
| 30 | void tegra_smmu_init(void) |
| 31 | { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 32 | uint32_t val, cb_idx, smmu_id, ctx_base; |
Varun Wadekar | 82b0b18 | 2019-09-26 08:26:41 -0700 | [diff] [blame^] | 33 | uint32_t num_smmu_devices = plat_get_num_smmu_devices(); |
Steven Kao | 7fd30f5 | 2017-07-25 11:29:46 +0800 | [diff] [blame] | 34 | |
Varun Wadekar | 82b0b18 | 2019-09-26 08:26:41 -0700 | [diff] [blame^] | 35 | for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 36 | /* Program the SMMU pagesize and reset CACHE_LOCK bit */ |
| 37 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 38 | val |= SMMU_GSR0_PGSIZE_64K; |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 39 | val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 40 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 41 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 42 | /* reset CACHE LOCK bit for NS Aux. Config. Register */ |
| 43 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 44 | val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 45 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 46 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 47 | /* disable TCU prefetch for all contexts */ |
| 48 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) |
| 49 | + SMMU_CBn_ACTLR; |
Varun Wadekar | 82b0b18 | 2019-09-26 08:26:41 -0700 | [diff] [blame^] | 50 | for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 51 | val = tegra_smmu_read_32(smmu_id, |
| 52 | ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 53 | val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 54 | tegra_smmu_write_32(smmu_id, ctx_base + |
| 55 | (SMMU_GSR0_PGSIZE_64K * cb_idx), val); |
| 56 | } |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 57 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 58 | /* set CACHE LOCK bit for NS Aux. Config. Register */ |
| 59 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 60 | val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 61 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 62 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 63 | /* set CACHE LOCK bit for S Aux. Config. Register */ |
| 64 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 65 | val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 66 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
| 67 | } |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 68 | } |
Varun Wadekar | 82b0b18 | 2019-09-26 08:26:41 -0700 | [diff] [blame^] | 69 | |
| 70 | /* |
| 71 | * Verify SMMU settings have not been altered during boot |
| 72 | */ |
| 73 | void tegra_smmu_verify(void) |
| 74 | { |
| 75 | uint32_t cb_idx, ctx_base, smmu_id, val; |
| 76 | uint32_t num_smmu_devices = plat_get_num_smmu_devices(); |
| 77 | uint32_t mismatch = 0U; |
| 78 | |
| 79 | for (smmu_id = 0U; smmu_id < num_smmu_devices; smmu_id++) { |
| 80 | /* check PGSIZE_64K bit inr S Aux. Config. Register */ |
| 81 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 82 | if (0U == (val & SMMU_GSR0_PGSIZE_64K)) { |
| 83 | ERROR("%s: PGSIZE_64K Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n", |
| 84 | __func__, smmu_id, val); |
| 85 | mismatch = MISMATCH_DETECTED; |
| 86 | } |
| 87 | |
| 88 | /* check CACHE LOCK bit in S Aux. Config. Register */ |
| 89 | if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) { |
| 90 | ERROR("%s: CACHE_LOCK Mismatch - smmu_id=%d, GSR0_SECURE_ACR=%x\n", |
| 91 | __func__, smmu_id, val); |
| 92 | mismatch = MISMATCH_DETECTED; |
| 93 | } |
| 94 | |
| 95 | /* check CACHE LOCK bit in NS Aux. Config. Register */ |
| 96 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
| 97 | if (0U == (val & SMMU_ACR_CACHE_LOCK_ENABLE_BIT)) { |
| 98 | ERROR("%s: Mismatch - smmu_id=%d, GNSR_ACR=%x\n", |
| 99 | __func__, smmu_id, val); |
| 100 | mismatch = MISMATCH_DETECTED; |
| 101 | } |
| 102 | |
| 103 | /* verify TCU prefetch for all contexts is disabled */ |
| 104 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) + |
| 105 | SMMU_CBn_ACTLR; |
| 106 | for (cb_idx = 0U; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { |
| 107 | val = tegra_smmu_read_32(smmu_id, |
| 108 | ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); |
| 109 | if (0U != (val & SMMU_CBn_ACTLR_CPRE_BIT)) { |
| 110 | ERROR("%s: Mismatch - smmu_id=%d, cb_idx=%d, GSR0_PGSIZE_64K=%x\n", |
| 111 | __func__, smmu_id, cb_idx, val); |
| 112 | mismatch = MISMATCH_DETECTED; |
| 113 | } |
| 114 | } |
| 115 | } |
| 116 | |
| 117 | /* Treat configuration mismatch as fatal */ |
| 118 | if ((mismatch == MISMATCH_DETECTED) && tegra_platform_is_silicon()) { |
| 119 | panic(); |
| 120 | } |
| 121 | } |