Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame^] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <string.h> |
| 10 | |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 11 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <common/bl_common.h> |
| 14 | #include <common/debug.h> |
| 15 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 16 | #include <smmu.h> |
Varun Wadekar | 93bed2a | 2016-03-18 13:07:33 -0700 | [diff] [blame] | 17 | #include <tegra_private.h> |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 18 | |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 19 | extern void memcpy16(void *dest, const void *src, unsigned int length); |
| 20 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 21 | /* SMMU IDs currently supported by the driver */ |
| 22 | enum { |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 23 | TEGRA_SMMU0 = 0U, |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 24 | TEGRA_SMMU1, |
| 25 | TEGRA_SMMU2 |
| 26 | }; |
| 27 | |
| 28 | static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off) |
| 29 | { |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 30 | uint32_t ret = 0U; |
| 31 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 32 | #if defined(TEGRA_SMMU0_BASE) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 33 | if (smmu_id == TEGRA_SMMU0) { |
| 34 | ret = mmio_read_32(TEGRA_SMMU0_BASE + (uint64_t)off); |
| 35 | } |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 36 | #endif |
| 37 | |
| 38 | #if defined(TEGRA_SMMU1_BASE) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 39 | if (smmu_id == TEGRA_SMMU1) { |
| 40 | ret = mmio_read_32(TEGRA_SMMU1_BASE + (uint64_t)off); |
| 41 | } |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 42 | #endif |
| 43 | |
| 44 | #if defined(TEGRA_SMMU2_BASE) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 45 | if (smmu_id == TEGRA_SMMU2) { |
| 46 | ret = mmio_read_32(TEGRA_SMMU2_BASE + (uint64_t)off); |
| 47 | } |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 48 | #endif |
| 49 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 50 | return ret; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 51 | } |
| 52 | |
| 53 | static void tegra_smmu_write_32(uint32_t smmu_id, |
| 54 | uint32_t off, uint32_t val) |
| 55 | { |
| 56 | #if defined(TEGRA_SMMU0_BASE) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 57 | if (smmu_id == TEGRA_SMMU0) { |
| 58 | mmio_write_32(TEGRA_SMMU0_BASE + (uint64_t)off, val); |
| 59 | } |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 60 | #endif |
| 61 | |
| 62 | #if defined(TEGRA_SMMU1_BASE) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 63 | if (smmu_id == TEGRA_SMMU1) { |
| 64 | mmio_write_32(TEGRA_SMMU1_BASE + (uint64_t)off, val); |
| 65 | } |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 66 | #endif |
| 67 | |
| 68 | #if defined(TEGRA_SMMU2_BASE) |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 69 | if (smmu_id == TEGRA_SMMU2) { |
| 70 | mmio_write_32(TEGRA_SMMU2_BASE + (uint64_t)off, val); |
| 71 | } |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 72 | #endif |
| 73 | } |
| 74 | |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame^] | 75 | #define SMMU_NUM_CONTEXTS 64U |
| 76 | #define SMMU_CONTEXT_BANK_MAX_IDX 64U |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 77 | |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 78 | /* |
| 79 | * Init SMMU during boot or "System Suspend" exit |
| 80 | */ |
| 81 | void tegra_smmu_init(void) |
| 82 | { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 83 | uint32_t val, cb_idx, smmu_id, ctx_base; |
Steven Kao | 7fd30f5 | 2017-07-25 11:29:46 +0800 | [diff] [blame] | 84 | uint32_t smmu_counter = plat_get_num_smmu_devices(); |
| 85 | |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 86 | for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) { |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 87 | /* Program the SMMU pagesize and reset CACHE_LOCK bit */ |
| 88 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
| 89 | val |= SMMU_GSR0_PGSIZE_64K; |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 90 | val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 91 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 92 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 93 | /* reset CACHE LOCK bit for NS Aux. Config. Register */ |
| 94 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 95 | val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 96 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 97 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 98 | /* disable TCU prefetch for all contexts */ |
| 99 | ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) |
| 100 | + SMMU_CBn_ACTLR; |
| 101 | for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) { |
| 102 | val = tegra_smmu_read_32(smmu_id, |
| 103 | ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx)); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 104 | val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 105 | tegra_smmu_write_32(smmu_id, ctx_base + |
| 106 | (SMMU_GSR0_PGSIZE_64K * cb_idx), val); |
| 107 | } |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 108 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 109 | /* set CACHE LOCK bit for NS Aux. Config. Register */ |
| 110 | val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 111 | val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 112 | tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val); |
Varun Wadekar | ea709c3 | 2016-04-20 17:14:15 -0700 | [diff] [blame] | 113 | |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 114 | /* set CACHE LOCK bit for S Aux. Config. Register */ |
| 115 | val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR); |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 116 | val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT; |
Pritesh Raithatha | 0de6e53 | 2017-01-24 13:49:46 +0530 | [diff] [blame] | 117 | tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val); |
| 118 | } |
Varun Wadekar | 3c95993 | 2016-03-03 13:09:08 -0800 | [diff] [blame] | 119 | } |