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Rupinderjit Singh820b3b62022-04-04 17:28:41 +01001# Copyright (c) 2021-2022, Arm Limited. All rights reserved.
Usama Ariff1513622021-04-09 17:07:41 +01002#
3# SPDX-License-Identifier: BSD-3-Clause
4#
5
Chris Kaye9272152021-09-28 15:52:14 +01006include common/fdt_wrappers.mk
7
Rupinderjit Singh820b3b62022-04-04 17:28:41 +01008ifeq ($(shell expr $(TARGET_PLATFORM) \<= 2), 0)
9 $(error TARGET_PLATFORM must be less than or equal to 2)
Usama Ariff1513622021-04-09 17:07:41 +010010endif
11
12CSS_LOAD_SCP_IMAGES := 1
13
14CSS_USE_SCMI_SDS_DRIVER := 1
15
16RAS_EXTENSION := 0
17
18SDEI_SUPPORT := 0
19
20EL3_EXCEPTION_HANDLING := 0
21
22HANDLE_EA_EL3_FIRST := 0
23
24# System coherency is managed in hardware
25HW_ASSISTED_COHERENCY := 1
26
27# When building for systems with hardware-assisted coherency, there's no need to
28# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
29USE_COHERENT_MEM := 0
30
31GIC_ENABLE_V4_EXTN := 1
32
33# GIC-600 configuration
34GICV3_SUPPORT_GIC600 := 1
35
Usama Arif1925c782021-08-20 20:53:34 +010036# Enable SVE
37ENABLE_SVE_FOR_NS := 1
38ENABLE_SVE_FOR_SWD := 1
Usama Ariff1513622021-04-09 17:07:41 +010039
Davidson K65361052021-10-13 18:49:41 +053040# enable trace buffer control registers access to NS by default
41ENABLE_TRBE_FOR_NS := 1
42
43# enable trace system registers access to NS by default
44ENABLE_SYS_REG_TRACE_FOR_NS := 1
45
46# enable trace filter control registers access to NS by default
47ENABLE_TRF_FOR_NS := 1
48
Usama Ariff1513622021-04-09 17:07:41 +010049# Include GICv3 driver files
50include drivers/arm/gic/v3/gicv3.mk
51
52ENT_GIC_SOURCES := ${GICV3_SOURCES} \
53 plat/common/plat_gicv3.c \
54 plat/arm/common/arm_gicv3.c
55
56override NEED_BL2U := no
57
58override ARM_PLAT_MT := 1
59
60TC_BASE = plat/arm/board/tc
61
62PLAT_INCLUDES += -I${TC_BASE}/include/
63
Usama Ariff1513622021-04-09 17:07:41 +010064# CPU libraries for TARGET_PLATFORM=0
65ifeq (${TARGET_PLATFORM}, 0)
Rupinderjit Singh820b3b62022-04-04 17:28:41 +010066TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \
67 lib/cpus/aarch64/cortex_a710.S \
Usama Ariff1513622021-04-09 17:07:41 +010068 lib/cpus/aarch64/cortex_x2.S
69endif
70
71# CPU libraries for TARGET_PLATFORM=1
72ifeq (${TARGET_PLATFORM}, 1)
Rupinderjit Singh820b3b62022-04-04 17:28:41 +010073TC_CPU_SOURCES += lib/cpus/aarch64/cortex_a510.S \
74 lib/cpus/aarch64/cortex_makalu.S \
Usama Ariff1513622021-04-09 17:07:41 +010075 lib/cpus/aarch64/cortex_makalu_elp_arm.S
76endif
77
Rupinderjit Singh820b3b62022-04-04 17:28:41 +010078# CPU libraries for TARGET_PLATFORM=2
79ifeq (${TARGET_PLATFORM}, 2)
80TC_CPU_SOURCES += lib/cpus/aarch64/cortex_hayes.S \
81 lib/cpus/aarch64/cortex_hunter.S
82endif
83
Usama Ariff1513622021-04-09 17:07:41 +010084INTERCONNECT_SOURCES := ${TC_BASE}/tc_interconnect.c
85
86PLAT_BL_COMMON_SOURCES += ${TC_BASE}/tc_plat.c \
87 ${TC_BASE}/include/tc_helpers.S
88
89BL1_SOURCES += ${INTERCONNECT_SOURCES} \
90 ${TC_CPU_SOURCES} \
91 ${TC_BASE}/tc_trusted_boot.c \
92 ${TC_BASE}/tc_err.c \
93 drivers/arm/sbsa/sbsa.c
94
95
96BL2_SOURCES += ${TC_BASE}/tc_security.c \
97 ${TC_BASE}/tc_err.c \
98 ${TC_BASE}/tc_trusted_boot.c \
Usama Arifa49bd492021-08-17 17:57:10 +010099 ${TC_BASE}/tc_bl2_setup.c \
Usama Ariff1513622021-04-09 17:07:41 +0100100 lib/utils/mem_region.c \
101 drivers/arm/tzc/tzc400.c \
102 plat/arm/common/arm_tzc400.c \
103 plat/arm/common/arm_nor_psci_mem_protect.c
104
105BL31_SOURCES += ${INTERCONNECT_SOURCES} \
106 ${TC_CPU_SOURCES} \
107 ${ENT_GIC_SOURCES} \
108 ${TC_BASE}/tc_bl31_setup.c \
109 ${TC_BASE}/tc_topology.c \
Usama Arifa49bd492021-08-17 17:57:10 +0100110 lib/fconf/fconf.c \
111 lib/fconf/fconf_dyn_cfg_getter.c \
Usama Ariff1513622021-04-09 17:07:41 +0100112 drivers/cfi/v2m/v2m_flash.c \
113 lib/utils/mem_region.c \
114 plat/arm/common/arm_nor_psci_mem_protect.c
115
Chris Kaye9272152021-09-28 15:52:14 +0100116BL31_SOURCES += ${FDT_WRAPPERS_SOURCES}
117
Usama Ariff1513622021-04-09 17:07:41 +0100118# Add the FDT_SOURCES and options for Dynamic Config
119FDT_SOURCES += ${TC_BASE}/fdts/${PLAT}_fw_config.dts \
120 ${TC_BASE}/fdts/${PLAT}_tb_fw_config.dts
121FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb
122TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
123
124# Add the FW_CONFIG to FIP and specify the same to certtool
125$(eval $(call TOOL_ADD_PAYLOAD,${FW_CONFIG},--fw-config,${FW_CONFIG}))
126# Add the TB_FW_CONFIG to FIP and specify the same to certtool
127$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config,${TB_FW_CONFIG}))
128
129ifeq (${SPD},spmd)
130ifeq ($(ARM_SPMC_MANIFEST_DTS),)
131ARM_SPMC_MANIFEST_DTS := ${TC_BASE}/fdts/${PLAT}_spmc_manifest.dts
132endif
133
134FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS}
135TC_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb
136
137# Add the TOS_FW_CONFIG to FIP and specify the same to certtool
138$(eval $(call TOOL_ADD_PAYLOAD,${TC_TOS_FW_CONFIG},--tos-fw-config,${TC_TOS_FW_CONFIG}))
139endif
140
141#Device tree
142TC_HW_CONFIG_DTS := fdts/tc.dts
143TC_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb
144FDT_SOURCES += ${TC_HW_CONFIG_DTS}
145$(eval TC_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC_HW_CONFIG_DTS)))
146
147# Add the HW_CONFIG to FIP and specify the same to certtool
148$(eval $(call TOOL_ADD_PAYLOAD,${TC_HW_CONFIG},--hw-config,${TC_HW_CONFIG}))
149
150override CTX_INCLUDE_AARCH32_REGS := 0
151
152override CTX_INCLUDE_PAUTH_REGS := 1
153
154override ENABLE_SPE_FOR_LOWER_ELS := 0
155
156override ENABLE_AMU := 1
Chris Kayc2d29ba2021-05-18 18:49:51 +0100157override ENABLE_AMU_AUXILIARY_COUNTERS := 1
158override ENABLE_AMU_FCONF := 1
159
160override ENABLE_MPMM := 1
161override ENABLE_MPMM_FCONF := 1
Usama Ariff1513622021-04-09 17:07:41 +0100162
163include plat/arm/common/arm_common.mk
164include plat/arm/css/common/css_common.mk
165include plat/arm/soc/common/soc_css.mk
166include plat/arm/board/common/board_common.mk