Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 1 | /* |
Michal Simek | 2a47faa | 2023-04-14 08:43:51 +0200 | [diff] [blame] | 2 | * Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved. |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* |
| 8 | * ZynqMP system level PM-API functions for clock control. |
| 9 | */ |
| 10 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 11 | #ifndef PM_API_CLOCK_H |
| 12 | #define PM_API_CLOCK_H |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 13 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <lib/utils_def.h> |
| 15 | |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 16 | #include "pm_common.h" |
| 17 | |
HariBabu Gattem | 9f9db61 | 2022-09-15 22:35:11 -0700 | [diff] [blame] | 18 | #define CLK_NAME_LEN (15U) |
| 19 | #define MAX_PARENTS (100U) |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 20 | #define CLK_NA_PARENT -1 |
| 21 | #define CLK_DUMMY_PARENT -2 |
| 22 | |
| 23 | /* Flags for parent id */ |
HariBabu Gattem | 9f9db61 | 2022-09-15 22:35:11 -0700 | [diff] [blame] | 24 | #define PARENT_CLK_SELF (0U) |
| 25 | #define PARENT_CLK_NODE1 (1U) |
| 26 | #define PARENT_CLK_NODE2 (2U) |
| 27 | #define PARENT_CLK_NODE3 (3U) |
| 28 | #define PARENT_CLK_NODE4 (4U) |
| 29 | #define PARENT_CLK_EXTERNAL (5U) |
| 30 | #define PARENT_CLK_MIO0_MIO77 (6U) |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 31 | |
| 32 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ |
| 33 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ |
| 34 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ |
| 35 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
| 36 | /* unused */ |
| 37 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
| 38 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
| 39 | #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ |
| 40 | #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ |
| 41 | #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */ |
| 42 | #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */ |
| 43 | #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */ |
| 44 | /* parents need enable during gate/ungate, set rate and re-parent */ |
| 45 | #define CLK_OPS_PARENT_ENABLE BIT(12) |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 46 | |
| 47 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
| 48 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
| 49 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
| 50 | #define CLK_DIVIDER_HIWORD_MASK BIT(3) |
| 51 | #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) |
| 52 | #define CLK_DIVIDER_READ_ONLY BIT(5) |
| 53 | #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) |
Rajan Vaja | 13d8a15 | 2019-03-15 14:19:26 +0530 | [diff] [blame] | 54 | #define CLK_FRAC BIT(8) |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 55 | |
| 56 | #define END_OF_CLK "END_OF_CLK" |
| 57 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 58 | //CLock Ids |
Jolly Shah | b4c9946 | 2019-01-02 12:40:17 -0800 | [diff] [blame] | 59 | enum clock_id { |
HariBabu Gattem | 6535f86 | 2022-09-22 02:45:16 -0700 | [diff] [blame] | 60 | CLK_IOPLL = (0U), |
| 61 | CLK_RPLL = (1U), |
| 62 | CLK_APLL = (2U), |
| 63 | CLK_DPLL = (3U), |
| 64 | CLK_VPLL = (4U), |
| 65 | CLK_IOPLL_TO_FPD = (5U), |
| 66 | CLK_RPLL_TO_FPD = (6U), |
| 67 | CLK_APLL_TO_LPD = (7U), |
| 68 | CLK_DPLL_TO_LPD = (8U), |
| 69 | CLK_VPLL_TO_LPD = (9U), |
| 70 | CLK_ACPU = (10U), |
| 71 | CLK_ACPU_HALF = (11U), |
| 72 | CLK_DBG_FPD = (12U), |
| 73 | CLK_DBG_LPD = (13U), |
| 74 | CLK_DBG_TRACE = (14U), |
| 75 | CLK_DBG_TSTMP = (15U), |
| 76 | CLK_DP_VIDEO_REF = (16U), |
| 77 | CLK_DP_AUDIO_REF = (17U), |
| 78 | CLK_DP_STC_REF = (18U), |
| 79 | CLK_GDMA_REF = (19U), |
| 80 | CLK_DPDMA_REF = (20U), |
| 81 | CLK_DDR_REF = (21U), |
| 82 | CLK_SATA_REF = (22U), |
| 83 | CLK_PCIE_REF = (23U), |
| 84 | CLK_GPU_REF = (24U), |
| 85 | CLK_GPU_PP0_REF = (25U), |
| 86 | CLK_GPU_PP1_REF = (26U), |
| 87 | CLK_TOPSW_MAIN = (27U), |
| 88 | CLK_TOPSW_LSBUS = (28U), |
| 89 | CLK_GTGREF0_REF = (29U), |
| 90 | CLK_LPD_SWITCH = (30U), |
| 91 | CLK_LPD_LSBUS = (31U), |
| 92 | CLK_USB0_BUS_REF = (32U), |
| 93 | CLK_USB1_BUS_REF = (33U), |
| 94 | CLK_USB3_DUAL_REF = (34U), |
| 95 | CLK_USB0 = (35U), |
| 96 | CLK_USB1 = (36U), |
| 97 | CLK_CPU_R5 = (37U), |
| 98 | CLK_CPU_R5_CORE = (38U), |
| 99 | CLK_CSU_SPB = (39U), |
| 100 | CLK_CSU_PLL = (40U), |
| 101 | CLK_PCAP = (41U), |
| 102 | CLK_IOU_SWITCH = (42U), |
| 103 | CLK_GEM_TSU_REF = (43U), |
| 104 | CLK_GEM_TSU = (44U), |
| 105 | CLK_GEM0_TX = (45U), |
| 106 | CLK_GEM1_TX = (46U), |
| 107 | CLK_GEM2_TX = (47U), |
| 108 | CLK_GEM3_TX = (48U), |
| 109 | CLK_GEM0_RX = (49U), |
| 110 | CLK_GEM1_RX = (50U), |
| 111 | CLK_GEM2_RX = (51U), |
| 112 | CLK_GEM3_RX = (52U), |
| 113 | CLK_QSPI_REF = (53U), |
| 114 | CLK_SDIO0_REF = (54U), |
| 115 | CLK_SDIO1_REF = (55U), |
| 116 | CLK_UART0_REF = (56U), |
| 117 | CLK_UART1_REF = (57U), |
| 118 | CLK_SPI0_REF = (58U), |
| 119 | CLK_SPI1_REF = (59U), |
| 120 | CLK_NAND_REF = (60U), |
| 121 | CLK_I2C0_REF = (61U), |
| 122 | CLK_I2C1_REF = (62U), |
| 123 | CLK_CAN0_REF = (63U), |
| 124 | CLK_CAN1_REF = (64U), |
| 125 | CLK_CAN0 = (65U), |
| 126 | CLK_CAN1 = (66U), |
| 127 | CLK_DLL_REF = (67U), |
| 128 | CLK_ADMA_REF = (68U), |
| 129 | CLK_TIMESTAMP_REF = (69U), |
| 130 | CLK_AMS_REF = (70U), |
| 131 | CLK_PL0_REF = (71U), |
| 132 | CLK_PL1_REF = (72U), |
| 133 | CLK_PL2_REF = (73U), |
| 134 | CLK_PL3_REF = (74U), |
| 135 | CLK_FPD_WDT = (75U), |
| 136 | CLK_IOPLL_INT = (76U), |
| 137 | CLK_IOPLL_PRE_SRC = (77U), |
| 138 | CLK_IOPLL_HALF = (78U), |
| 139 | CLK_IOPLL_INT_MUX = (79U), |
| 140 | CLK_IOPLL_POST_SRC = (80U), |
| 141 | CLK_RPLL_INT = (81U), |
| 142 | CLK_RPLL_PRE_SRC = (82U), |
| 143 | CLK_RPLL_HALF = (83U), |
| 144 | CLK_RPLL_INT_MUX = (84U), |
| 145 | CLK_RPLL_POST_SRC = (85U), |
| 146 | CLK_APLL_INT = (86U), |
| 147 | CLK_APLL_PRE_SRC = (87U), |
| 148 | CLK_APLL_HALF = (88U), |
| 149 | CLK_APLL_INT_MUX = (89U), |
| 150 | CLK_APLL_POST_SRC = (90U), |
| 151 | CLK_DPLL_INT = (91U), |
| 152 | CLK_DPLL_PRE_SRC = (92U), |
| 153 | CLK_DPLL_HALF = (93U), |
| 154 | CLK_DPLL_INT_MUX = (94U), |
| 155 | CLK_DPLL_POST_SRC = (95U), |
| 156 | CLK_VPLL_INT = (96U), |
| 157 | CLK_VPLL_PRE_SRC = (97U), |
| 158 | CLK_VPLL_HALF = (98U), |
| 159 | CLK_VPLL_INT_MUX = (99U), |
| 160 | CLK_VPLL_POST_SRC = (100U), |
| 161 | CLK_CAN0_MIO = (101U), |
| 162 | CLK_CAN1_MIO = (102U), |
| 163 | CLK_ACPU_FULL = (103U), |
| 164 | CLK_GEM0_REF = (104U), |
| 165 | CLK_GEM1_REF = (105U), |
| 166 | CLK_GEM2_REF = (106U), |
| 167 | CLK_GEM3_REF = (107U), |
| 168 | CLK_GEM0_REF_UNGATED = (108U), |
| 169 | CLK_GEM1_REF_UNGATED = (109U), |
| 170 | CLK_GEM2_REF_UNGATED = (110U), |
| 171 | CLK_GEM3_REF_UNGATED = (111U), |
| 172 | CLK_LPD_WDT = (112U), |
| 173 | END_OF_OUTPUT_CLKS = (113U), |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 174 | }; |
| 175 | |
HariBabu Gattem | 6535f86 | 2022-09-22 02:45:16 -0700 | [diff] [blame] | 176 | #define CLK_MAX_OUTPUT_CLK END_OF_OUTPUT_CLKS |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 177 | |
| 178 | //External clock ids |
| 179 | enum { |
| 180 | EXT_CLK_PSS_REF = END_OF_OUTPUT_CLKS, |
HariBabu Gattem | 6535f86 | 2022-09-22 02:45:16 -0700 | [diff] [blame] | 181 | EXT_CLK_VIDEO = (114U), |
| 182 | EXT_CLK_PSS_ALT_REF = (115U), |
| 183 | EXT_CLK_AUX_REF = (116U), |
| 184 | EXT_CLK_GT_CRX_REF = (117U), |
| 185 | EXT_CLK_SWDT0 = (118U), |
| 186 | EXT_CLK_SWDT1 = (119U), |
| 187 | EXT_CLK_GEM0_TX_EMIO = (120U), |
| 188 | EXT_CLK_GEM1_TX_EMIO = (121U), |
| 189 | EXT_CLK_GEM2_TX_EMIO = (122U), |
| 190 | EXT_CLK_GEM3_TX_EMIO = (123U), |
| 191 | EXT_CLK_GEM0_RX_EMIO = (124U), |
| 192 | EXT_CLK_GEM1_RX_EMIO = (125U), |
| 193 | EXT_CLK_GEM2_RX_EMIO = (126U), |
| 194 | EXT_CLK_GEM3_RX_EMIO = (127U), |
| 195 | EXT_CLK_MIO50_OR_MIO51 = (128U), |
| 196 | EXT_CLK_MIO0 = (129U), |
| 197 | EXT_CLK_MIO1 = (130U), |
| 198 | EXT_CLK_MIO2 = (131U), |
| 199 | EXT_CLK_MIO3 = (132U), |
| 200 | EXT_CLK_MIO4 = (133U), |
| 201 | EXT_CLK_MIO5 = (134U), |
| 202 | EXT_CLK_MIO6 = (135U), |
| 203 | EXT_CLK_MIO7 = (136U), |
| 204 | EXT_CLK_MIO8 = (137U), |
| 205 | EXT_CLK_MIO9 = (138U), |
| 206 | EXT_CLK_MIO10 = (139U), |
| 207 | EXT_CLK_MIO11 = (140U), |
| 208 | EXT_CLK_MIO12 = (141U), |
| 209 | EXT_CLK_MIO13 = (142U), |
| 210 | EXT_CLK_MIO14 = (143U), |
| 211 | EXT_CLK_MIO15 = (144U), |
| 212 | EXT_CLK_MIO16 = (145U), |
| 213 | EXT_CLK_MIO17 = (146U), |
| 214 | EXT_CLK_MIO18 = (147U), |
| 215 | EXT_CLK_MIO19 = (148U), |
| 216 | EXT_CLK_MIO20 = (149U), |
| 217 | EXT_CLK_MIO21 = (150U), |
| 218 | EXT_CLK_MIO22 = (151U), |
| 219 | EXT_CLK_MIO23 = (152U), |
| 220 | EXT_CLK_MIO24 = (153U), |
| 221 | EXT_CLK_MIO25 = (154U), |
| 222 | EXT_CLK_MIO26 = (155U), |
| 223 | EXT_CLK_MIO27 = (156U), |
| 224 | EXT_CLK_MIO28 = (157U), |
| 225 | EXT_CLK_MIO29 = (158U), |
| 226 | EXT_CLK_MIO30 = (159U), |
| 227 | EXT_CLK_MIO31 = (160U), |
| 228 | EXT_CLK_MIO32 = (161U), |
| 229 | EXT_CLK_MIO33 = (162U), |
| 230 | EXT_CLK_MIO34 = (163U), |
| 231 | EXT_CLK_MIO35 = (164U), |
| 232 | EXT_CLK_MIO36 = (165U), |
| 233 | EXT_CLK_MIO37 = (166U), |
| 234 | EXT_CLK_MIO38 = (167U), |
| 235 | EXT_CLK_MIO39 = (168U), |
| 236 | EXT_CLK_MIO40 = (169U), |
| 237 | EXT_CLK_MIO41 = (170U), |
| 238 | EXT_CLK_MIO42 = (171U), |
| 239 | EXT_CLK_MIO43 = (172U), |
| 240 | EXT_CLK_MIO44 = (173U), |
| 241 | EXT_CLK_MIO45 = (174U), |
| 242 | EXT_CLK_MIO46 = (175U), |
| 243 | EXT_CLK_MIO47 = (176U), |
| 244 | EXT_CLK_MIO48 = (177U), |
| 245 | EXT_CLK_MIO49 = (178U), |
| 246 | EXT_CLK_MIO50 = (179U), |
| 247 | EXT_CLK_MIO51 = (180U), |
| 248 | EXT_CLK_MIO52 = (181U), |
| 249 | EXT_CLK_MIO53 = (182U), |
| 250 | EXT_CLK_MIO54 = (183U), |
| 251 | EXT_CLK_MIO55 = (184U), |
| 252 | EXT_CLK_MIO56 = (185U), |
| 253 | EXT_CLK_MIO57 = (186U), |
| 254 | EXT_CLK_MIO58 = (187U), |
| 255 | EXT_CLK_MIO59 = (188U), |
| 256 | EXT_CLK_MIO60 = (189U), |
| 257 | EXT_CLK_MIO61 = (190U), |
| 258 | EXT_CLK_MIO62 = (191U), |
| 259 | EXT_CLK_MIO63 = (192U), |
| 260 | EXT_CLK_MIO64 = (193U), |
| 261 | EXT_CLK_MIO65 = (194U), |
| 262 | EXT_CLK_MIO66 = (195U), |
| 263 | EXT_CLK_MIO67 = (196U), |
| 264 | EXT_CLK_MIO68 = (197U), |
| 265 | EXT_CLK_MIO69 = (198U), |
| 266 | EXT_CLK_MIO70 = (199U), |
| 267 | EXT_CLK_MIO71 = (200U), |
| 268 | EXT_CLK_MIO72 = (201U), |
| 269 | EXT_CLK_MIO73 = (202U), |
| 270 | EXT_CLK_MIO74 = (203U), |
| 271 | EXT_CLK_MIO75 = (204U), |
| 272 | EXT_CLK_MIO76 = (205U), |
| 273 | EXT_CLK_MIO77 = (206U), |
| 274 | END_OF_CLKS = (207U), |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 275 | }; |
| 276 | |
HariBabu Gattem | 6535f86 | 2022-09-22 02:45:16 -0700 | [diff] [blame] | 277 | #define CLK_MAX END_OF_CLKS |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 278 | |
Jolly Shah | 69fb5bf | 2018-02-07 16:25:41 -0800 | [diff] [blame] | 279 | //CLock types |
| 280 | #define CLK_TYPE_OUTPUT 0U |
| 281 | #define CLK_TYPE_EXTERNAL 1U |
| 282 | |
| 283 | //Topology types |
| 284 | #define TYPE_INVALID 0U |
| 285 | #define TYPE_MUX 1U |
| 286 | #define TYPE_PLL 2U |
| 287 | #define TYPE_FIXEDFACTOR 3U |
| 288 | #define TYPE_DIV1 4U |
| 289 | #define TYPE_DIV2 5U |
| 290 | #define TYPE_GATE 6U |
| 291 | |
Jolly Shah | a520980 | 2019-01-04 11:45:59 -0800 | [diff] [blame] | 292 | struct pm_pll; |
| 293 | struct pm_pll *pm_clock_get_pll(enum clock_id clock_id); |
Jolly Shah | 407fc0a | 2019-01-04 11:57:40 -0800 | [diff] [blame] | 294 | struct pm_pll *pm_clock_get_pll_by_related_clk(enum clock_id clock_id); |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 295 | uint8_t pm_clock_has_div(uint32_t clock_id, enum pm_clock_div_id div_id); |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 296 | |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 297 | void pm_api_clock_get_name(uint32_t clock_id, char *name); |
| 298 | enum pm_ret_status pm_api_clock_get_num_clocks(uint32_t *nclocks); |
| 299 | enum pm_ret_status pm_api_clock_get_topology(uint32_t clock_id, |
| 300 | uint32_t index, |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 301 | uint32_t *topology); |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 302 | enum pm_ret_status pm_api_clock_get_fixedfactor_params(uint32_t clock_id, |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 303 | uint32_t *mul, |
| 304 | uint32_t *div); |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 305 | enum pm_ret_status pm_api_clock_get_parents(uint32_t clock_id, |
| 306 | uint32_t index, |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 307 | uint32_t *parents); |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 308 | enum pm_ret_status pm_api_clock_get_attributes(uint32_t clock_id, |
Rajan Vaja | 3511613 | 2018-01-17 02:39:25 -0800 | [diff] [blame] | 309 | uint32_t *attr); |
Rajan Vaja | b34deca | 2019-03-20 01:13:21 +0530 | [diff] [blame] | 310 | enum pm_ret_status pm_api_clock_get_max_divisor(enum clock_id clock_id, |
| 311 | uint8_t div_type, |
| 312 | uint32_t *max_div); |
Jolly Shah | b4c9946 | 2019-01-02 12:40:17 -0800 | [diff] [blame] | 313 | |
| 314 | enum pm_ret_status pm_clock_get_pll_node_id(enum clock_id clock_id, |
| 315 | enum pm_node_id *node_id); |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 316 | enum pm_ret_status pm_clock_id_is_valid(uint32_t clock_id); |
Jolly Shah | b4c9946 | 2019-01-02 12:40:17 -0800 | [diff] [blame] | 317 | |
Jolly Shah | a520980 | 2019-01-04 11:45:59 -0800 | [diff] [blame] | 318 | enum pm_ret_status pm_clock_pll_enable(struct pm_pll *pll); |
Jolly Shah | a9057a0 | 2019-01-02 12:54:40 -0800 | [diff] [blame] | 319 | enum pm_ret_status pm_clock_pll_disable(struct pm_pll *pll); |
Jolly Shah | 99e8ac9 | 2019-01-02 12:55:41 -0800 | [diff] [blame] | 320 | enum pm_ret_status pm_clock_pll_get_state(struct pm_pll *pll, |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 321 | uint32_t *state); |
Jolly Shah | 407fc0a | 2019-01-04 11:57:40 -0800 | [diff] [blame] | 322 | enum pm_ret_status pm_clock_pll_set_parent(struct pm_pll *pll, |
| 323 | enum clock_id clock_id, |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 324 | uint32_t parent_index); |
Jolly Shah | 7c8e79c | 2019-01-02 13:44:25 -0800 | [diff] [blame] | 325 | enum pm_ret_status pm_clock_pll_get_parent(struct pm_pll *pll, |
| 326 | enum clock_id clock_id, |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 327 | uint32_t *parent_index); |
Jolly Shah | cb5bc75 | 2019-01-02 12:46:46 -0800 | [diff] [blame] | 328 | enum pm_ret_status pm_clock_set_pll_mode(enum clock_id clock_id, |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 329 | uint32_t mode); |
Jolly Shah | 77eb52f | 2019-01-02 12:49:21 -0800 | [diff] [blame] | 330 | enum pm_ret_status pm_clock_get_pll_mode(enum clock_id clock_id, |
Venkatesh Yadav Abbarapu | e7c4538 | 2022-05-19 14:49:49 +0530 | [diff] [blame] | 331 | uint32_t *mode); |
Rajan Vaja | d98455b | 2018-01-17 02:39:26 -0800 | [diff] [blame] | 332 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 333 | #endif /* PM_API_CLOCK_H */ |