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git01.mediatek.com / filogic / atf / d98455b1020ef27465c203745b591c1ea18581bb / . / plat / xilinx / zynqmp / pm_service / pm_api_clock.h
blob: 666eda5777c2d647c1c145fff2bc977d8515006a [file] [log] [blame]
Rajan Vaja35116132018-01-17 02:39:25 -0800[diff] [blame]1/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7/*
8 * ZynqMP system level PM-API functions for clock control.
9 */
10
11#ifndef _PM_API_CLOCK_H_
12#define _PM_API_CLOCK_H_
13
Rajan Vajad98455b2018-01-17 02:39:26 -0800[diff] [blame^]14#include <utils_def.h>
Rajan Vaja35116132018-01-17 02:39:25 -0800[diff] [blame]15#include "pm_common.h"
16
17#define CLK_NAME_LEN 15
Rajan Vajad98455b2018-01-17 02:39:26 -0800[diff] [blame^]18#define MAX_PARENTS 100
19#define CLK_NA_PARENT -1
20#define CLK_DUMMY_PARENT -2
21
22/* Flags for parent id */
23#define PARENT_CLK_SELF 0
24#define PARENT_CLK_NODE1 1
25#define PARENT_CLK_NODE2 2
26#define PARENT_CLK_NODE3 3
27#define PARENT_CLK_NODE4 4
28#define PARENT_CLK_EXTERNAL 5
29#define PARENT_CLK_MIO0_MIO77 6
30
31#define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
32#define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
33#define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
34#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
35/* unused */
36#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
37#define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
38#define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
39#define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
40#define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
41#define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
42#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
43/* parents need enable during gate/ungate, set rate and re-parent */
44#define CLK_OPS_PARENT_ENABLE BIT(12)
45#define CLK_FRAC BIT(13)
46
47#define CLK_DIVIDER_ONE_BASED BIT(0)
48#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
49#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
50#define CLK_DIVIDER_HIWORD_MASK BIT(3)
51#define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
52#define CLK_DIVIDER_READ_ONLY BIT(5)
53#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
54
55#define END_OF_CLK "END_OF_CLK"
56
57enum clock_ids {
58 CLK_IOPLL,
59 CLK_RPLL,
60 CLK_APLL,
61 CLK_DPLL,
62 CLK_VPLL,
63 CLK_IOPLL_TO_FPD,
64 CLK_RPLL_TO_FPD,
65 CLK_APLL_TO_LPD,
66 CLK_DPLL_TO_LPD,
67 CLK_VPLL_TO_LPD,
68 CLK_ACPU,
69 CLK_ACPU_HALF,
70 CLK_DBG_FPD,
71 CLK_DBG_LPD,
72 CLK_DBG_TRACE,
73 CLK_DBG_TSTMP,
74 CLK_DP_VIDEO_REF,
75 CLK_DP_AUDIO_REF,
76 CLK_DP_STC_REF,
77 CLK_GDMA_REF,
78 CLK_DPDMA_REF,
79 CLK_DDR_REF,
80 CLK_SATA_REF,
81 CLK_PCIE_REF,
82 CLK_GPU_REF,
83 CLK_GPU_PP0_REF,
84 CLK_GPU_PP1_REF,
85 CLK_TOPSW_MAIN,
86 CLK_TOPSW_LSBUS,
87 CLK_GTGREF0_REF,
88 CLK_LPD_SWITCH,
89 CLK_LPD_LSBUS,
90 CLK_USB0_BUS_REF,
91 CLK_USB1_BUS_REF,
92 CLK_USB3_DUAL_REF,
93 CLK_USB0,
94 CLK_USB1,
95 CLK_CPU_R5,
96 CLK_CPU_R5_CORE,
97 CLK_CSU_SPB,
98 CLK_CSU_PLL,
99 CLK_PCAP,
100 CLK_IOU_SWITCH,
101 CLK_GEM_TSU_REF,
102 CLK_GEM_TSU,
103 CLK_GEM0_REF,
104 CLK_GEM1_REF,
105 CLK_GEM2_REF,
106 CLK_GEM3_REF,
107 CLK_GEM0_TX,
108 CLK_GEM1_TX,
109 CLK_GEM2_TX,
110 CLK_GEM3_TX,
111 CLK_QSPI_REF,
112 CLK_SDIO0_REF,
113 CLK_SDIO1_REF,
114 CLK_UART0_REF,
115 CLK_UART1_REF,
116 CLK_SPI0_REF,
117 CLK_SPI1_REF,
118 CLK_NAND_REF,
119 CLK_I2C0_REF,
120 CLK_I2C1_REF,
121 CLK_CAN0_REF,
122 CLK_CAN1_REF,
123 CLK_CAN0,
124 CLK_CAN1,
125 CLK_DLL_REF,
126 CLK_ADMA_REF,
127 CLK_TIMESTAMP_REF,
128 CLK_AMS_REF,
129 CLK_PL0_REF,
130 CLK_PL1_REF,
131 CLK_PL2_REF,
132 CLK_PL3_REF,
133 CLK_WDT,
134 CLK_IOPLL_INT,
135 CLK_IOPLL_PRE_SRC,
136 CLK_IOPLL_HALF,
137 CLK_IOPLL_INT_MUX,
138 CLK_IOPLL_POST_SRC,
139 CLK_RPLL_INT,
140 CLK_RPLL_PRE_SRC,
141 CLK_RPLL_HALF,
142 CLK_RPLL_INT_MUX,
143 CLK_RPLL_POST_SRC,
144 CLK_APLL_INT,
145 CLK_APLL_PRE_SRC,
146 CLK_APLL_HALF,
147 CLK_APLL_INT_MUX,
148 CLK_APLL_POST_SRC,
149 CLK_DPLL_INT,
150 CLK_DPLL_PRE_SRC,
151 CLK_DPLL_HALF,
152 CLK_DPLL_INT_MUX,
153 CLK_DPLL_POST_SRC,
154 CLK_VPLL_INT,
155 CLK_VPLL_PRE_SRC,
156 CLK_VPLL_HALF,
157 CLK_VPLL_INT_MUX,
158 CLK_VPLL_POST_SRC,
159 CLK_CAN0_MIO,
160 CLK_CAN1_MIO,
161 CLK_MAX_OUTPUT_CLK,
162};
163
164enum external_clk_ids {
165 EXT_CLK_PSS_REF = CLK_MAX_OUTPUT_CLK,
166 EXT_CLK_VIDEO,
167 EXT_CLK_PSS_ALT_REF,
168 EXT_CLK_AUX_REF,
169 EXT_CLK_GT_CRX_REF,
170 EXT_CLK_SWDT0,
171 EXT_CLK_SWDT1,
172 EXT_CLK_GEM0_EMIO,
173 EXT_CLK_GEM1_EMIO,
174 EXT_CLK_GEM2_EMIO,
175 EXT_CLK_GEM3_EMIO,
176 EXT_CLK_MIO50_OR_MIO51,
177 EXT_CLK_MIO0,
178 EXT_CLK_MIO1,
179 EXT_CLK_MIO2,
180 EXT_CLK_MIO3,
181 EXT_CLK_MIO4,
182 EXT_CLK_MIO5,
183 EXT_CLK_MIO6,
184 EXT_CLK_MIO7,
185 EXT_CLK_MIO8,
186 EXT_CLK_MIO9,
187 EXT_CLK_MIO10,
188 EXT_CLK_MIO11,
189 EXT_CLK_MIO12,
190 EXT_CLK_MIO13,
191 EXT_CLK_MIO14,
192 EXT_CLK_MIO15,
193 EXT_CLK_MIO16,
194 EXT_CLK_MIO17,
195 EXT_CLK_MIO18,
196 EXT_CLK_MIO19,
197 EXT_CLK_MIO20,
198 EXT_CLK_MIO21,
199 EXT_CLK_MIO22,
200 EXT_CLK_MIO23,
201 EXT_CLK_MIO24,
202 EXT_CLK_MIO25,
203 EXT_CLK_MIO26,
204 EXT_CLK_MIO27,
205 EXT_CLK_MIO28,
206 EXT_CLK_MIO29,
207 EXT_CLK_MIO30,
208 EXT_CLK_MIO31,
209 EXT_CLK_MIO32,
210 EXT_CLK_MIO33,
211 EXT_CLK_MIO34,
212 EXT_CLK_MIO35,
213 EXT_CLK_MIO36,
214 EXT_CLK_MIO37,
215 EXT_CLK_MIO38,
216 EXT_CLK_MIO39,
217 EXT_CLK_MIO40,
218 EXT_CLK_MIO41,
219 EXT_CLK_MIO42,
220 EXT_CLK_MIO43,
221 EXT_CLK_MIO44,
222 EXT_CLK_MIO45,
223 EXT_CLK_MIO46,
224 EXT_CLK_MIO47,
225 EXT_CLK_MIO48,
226 EXT_CLK_MIO49,
227 EXT_CLK_MIO50,
228 EXT_CLK_MIO51,
229 EXT_CLK_MIO52,
230 EXT_CLK_MIO53,
231 EXT_CLK_MIO54,
232 EXT_CLK_MIO55,
233 EXT_CLK_MIO56,
234 EXT_CLK_MIO57,
235 EXT_CLK_MIO58,
236 EXT_CLK_MIO59,
237 EXT_CLK_MIO60,
238 EXT_CLK_MIO61,
239 EXT_CLK_MIO62,
240 EXT_CLK_MIO63,
241 EXT_CLK_MIO64,
242 EXT_CLK_MIO65,
243 EXT_CLK_MIO66,
244 EXT_CLK_MIO67,
245 EXT_CLK_MIO68,
246 EXT_CLK_MIO69,
247 EXT_CLK_MIO70,
248 EXT_CLK_MIO71,
249 EXT_CLK_MIO72,
250 EXT_CLK_MIO73,
251 EXT_CLK_MIO74,
252 EXT_CLK_MIO75,
253 EXT_CLK_MIO76,
254 EXT_CLK_MIO77,
255 CLK_MAX,
256};
257
258enum clk_type {
259 CLK_TYPE_OUTPUT,
260 CLK_TYPE_EXTERNAL,
261};
262
263enum topology_type {
264 TYPE_INVALID,
265 TYPE_MUX,
266 TYPE_PLL,
267 TYPE_FIXEDFACTOR,
268 TYPE_DIV1,
269 TYPE_DIV2,
270 TYPE_GATE,
271};
Rajan Vaja35116132018-01-17 02:39:25 -0800[diff] [blame]272
273enum pm_ret_status pm_api_clock_get_name(unsigned int clock_id, char *name);
274enum pm_ret_status pm_api_clock_get_topology(unsigned int clock_id,
275 unsigned int index,
276 uint32_t *topology);
277enum pm_ret_status pm_api_clock_get_fixedfactor_params(unsigned int clock_id,
278 uint32_t *mul,
279 uint32_t *div);
280enum pm_ret_status pm_api_clock_get_parents(unsigned int clock_id,
281 unsigned int index,
282 uint32_t *parents);
283enum pm_ret_status pm_api_clock_get_attributes(unsigned int clock_id,
284 uint32_t *attr);
285enum pm_ret_status pm_api_clock_enable(unsigned int clock_id);
286enum pm_ret_status pm_api_clock_disable(unsigned int clock_id);
287enum pm_ret_status pm_api_clock_getstate(unsigned int clock_id,
288 unsigned int *state);
289enum pm_ret_status pm_api_clock_setdivider(unsigned int clock_id,
290 unsigned int divider);
291enum pm_ret_status pm_api_clock_getdivider(unsigned int clock_id,
292 unsigned int *divider);
293enum pm_ret_status pm_api_clock_setrate(unsigned int clock_id,
294 uint64_t rate);
295enum pm_ret_status pm_api_clock_getrate(unsigned int clock_id,
296 uint64_t *rate);
297enum pm_ret_status pm_api_clock_setparent(unsigned int clock_id,
298 unsigned int parent_idx);
299enum pm_ret_status pm_api_clock_getparent(unsigned int clock_id,
300 unsigned int *parent_idx);
301enum pm_ret_status pm_api_clk_set_pll_mode(unsigned int pll,
302 unsigned int mode);
303enum pm_ret_status pm_api_clk_get_pll_mode(unsigned int pll,
304 unsigned int *mode);
305enum pm_ret_status pm_api_clk_set_pll_frac_data(unsigned int pll,
306 unsigned int data);
307enum pm_ret_status pm_api_clk_get_pll_frac_data(unsigned int pll,
308 unsigned int *data);
Rajan Vajad98455b2018-01-17 02:39:26 -0800[diff] [blame^]309
Rajan Vaja35116132018-01-17 02:39:25 -0800[diff] [blame]310#endif /* _PM_API_CLOCK_H_ */