blob: ac34450a7630ed5e363ce014f9e7f3fb61d9a406 [file] [log] [blame]
Nariman Poushinc703f902018-03-07 10:29:57 +00001#
Ambroise Vincent322971d2019-04-11 13:45:18 +01002# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Nariman Poushinc703f902018-03-07 10:29:57 +00003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
Chris Kayf9c4cf42019-04-23 16:31:06 +01007CSS_USE_SCMI_SDS_DRIVER := 1
8
Nariman Poushinc703f902018-03-07 10:29:57 +00009CSS_SGM_BASE := plat/arm/css/sgm
10
11PLAT_INCLUDES := -I${CSS_SGM_BASE}/include
12
13PLAT_BL_COMMON_SOURCES := ${CSS_SGM_BASE}/sgm_mmap_config.c \
14 ${CSS_SGM_BASE}/aarch64/css_sgm_helpers.S
15
16SECURITY_SOURCES := drivers/arm/tzc/tzc_dmc500.c \
Ambroise Vincent322971d2019-04-11 13:45:18 +010017 plat/arm/common/arm_tzc_dmc500.c \
Nariman Poushinc703f902018-03-07 10:29:57 +000018 ${CSS_SGM_BASE}/sgm_security.c
19
20SGM_CPU_SOURCES := lib/cpus/aarch64/cortex_a55.S \
21 lib/cpus/aarch64/cortex_a75.S
22
23INTERCONNECT_SOURCES := ${CSS_SGM_BASE}/sgm_interconnect.c
24
25SGM_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
26 drivers/arm/gic/v3/gicv3_main.c \
27 drivers/arm/gic/v3/gicv3_helpers.c \
28 plat/common/plat_gicv3.c \
29 plat/arm/common/arm_gicv3.c \
30 drivers/arm/gic/v3/gic600.c \
31 drivers/arm/gic/v3/arm_gicv3_common.c
32
33BL1_SOURCES += $(SGM_CPU_SOURCES) \
34 ${INTERCONNECT_SOURCES} \
Ambroise Vincent322971d2019-04-11 13:45:18 +010035 ${CSS_SGM_BASE}/sgm_bl1_setup.c \
Aditya Angadi20b48412019-04-16 11:29:14 +053036 ${CSS_SGM_BASE}/sgm_plat_config.c \
37 drivers/arm/sp805/sp805.c
Nariman Poushinc703f902018-03-07 10:29:57 +000038
Ambroise Vincent322971d2019-04-11 13:45:18 +010039BL2_SOURCES += ${SECURITY_SOURCES} \
40 ${CSS_SGM_BASE}/sgm_plat_config.c
Nariman Poushinc703f902018-03-07 10:29:57 +000041
42BL2U_SOURCES += ${SECURITY_SOURCES}
43
44BL31_SOURCES += $(SGM_CPU_SOURCES) \
45 ${INTERCONNECT_SOURCES} \
46 ${SECURITY_SOURCES} \
47 ${SGM_GIC_SOURCES} \
Ambroise Vincent322971d2019-04-11 13:45:18 +010048 ${CSS_SGM_BASE}/sgm_topology.c \
Nariman Poushinc703f902018-03-07 10:29:57 +000049 ${CSS_SGM_BASE}/sgm_bl31_setup.c \
50 ${CSS_SGM_BASE}/sgm_plat_config.c
51
Deepak Pandeyb0971f92018-05-25 12:43:30 +053052ifneq (${RESET_TO_BL31},0)
Sandrine Bailleux1e32d322019-01-07 15:35:37 +010053 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Deepak Pandeyb0971f92018-05-25 12:43:30 +053054 Please set RESET_TO_BL31 to 0.")
55endif
56
Nariman Poushinc703f902018-03-07 10:29:57 +000057# sgm uses CCI-500 as Cache Coherent Interconnect
58ARM_CCI_PRODUCT_ID := 500
59
Nariman Poushinc703f902018-03-07 10:29:57 +000060# System coherency is managed in hardware
61HW_ASSISTED_COHERENCY := 1
62
63# When building for systems with hardware-assisted coherency, there's no need to
64# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
65USE_COHERENT_MEM := 0
66
67override ARM_PLAT_MT := 1
68
69$(eval $(call add_define,SGM_PLAT))
70
71include plat/arm/common/arm_common.mk
72include plat/arm/board/common/board_common.mk
73include plat/arm/css/common/css_common.mk
74include plat/arm/soc/common/soc_css.mk