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Yann Gautieree8f5422019-02-14 11:13:25 +01001/*
Yann Gautiered6515d2021-03-08 15:03:35 +01002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Yann Gautieree8f5422019-02-14 11:13:25 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Yann Gautiere97b6632019-04-19 10:48:36 +02008#include <errno.h>
Yann Gautieree8f5422019-02-14 11:13:25 +01009
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/debug.h>
Yann Gautier3d78a2e2019-02-14 11:01:20 +010014#include <drivers/st/stm32mp_clkfunc.h>
Yann Gautiered6515d2021-03-08 15:03:35 +010015#include <lib/smccc.h>
Yann Gautiera55169b2020-01-10 18:18:59 +010016#include <lib/xlat_tables/xlat_tables_v2.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010017#include <plat/common/platform.h>
Yann Gautiered6515d2021-03-08 15:03:35 +010018#include <services/arm_arch_svc.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010019
20uintptr_t plat_get_ns_image_entrypoint(void)
21{
22 return BL33_BASE;
23}
24
25unsigned int plat_get_syscnt_freq2(void)
26{
27 return read_cntfrq_el0();
28}
29
30static uintptr_t boot_ctx_address;
31
Yann Gautiera2e2a302019-02-14 11:13:39 +010032void stm32mp_save_boot_ctx_address(uintptr_t address)
Yann Gautieree8f5422019-02-14 11:13:25 +010033{
34 boot_ctx_address = address;
35}
36
Yann Gautiera2e2a302019-02-14 11:13:39 +010037uintptr_t stm32mp_get_boot_ctx_address(void)
Yann Gautieree8f5422019-02-14 11:13:25 +010038{
39 return boot_ctx_address;
40}
41
Yann Gautier3d78a2e2019-02-14 11:01:20 +010042uintptr_t stm32mp_ddrctrl_base(void)
43{
Yann Gautiera18f61b2020-05-05 17:58:40 +020044 return DDRCTRL_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010045}
46
47uintptr_t stm32mp_ddrphyc_base(void)
48{
Yann Gautiera18f61b2020-05-05 17:58:40 +020049 return DDRPHYC_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010050}
51
52uintptr_t stm32mp_pwr_base(void)
53{
Yann Gautiera18f61b2020-05-05 17:58:40 +020054 return PWR_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010055}
56
57uintptr_t stm32mp_rcc_base(void)
58{
Yann Gautiera18f61b2020-05-05 17:58:40 +020059 return RCC_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010060}
61
Yann Gautierf540a592019-05-22 19:13:51 +020062bool stm32mp_lock_available(void)
63{
64 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
65
66 /* The spinlocks are used only when MMU and data cache are enabled */
67 return (read_sctlr() & c_m_bits) == c_m_bits;
68}
69
Yann Gautiere97b6632019-04-19 10:48:36 +020070int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
71{
72 uint32_t i;
73 uint32_t img_checksum = 0U;
74
75 /*
76 * Check header/payload validity:
77 * - Header magic
78 * - Header version
79 * - Payload checksum
80 */
81 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
82 ERROR("Header magic\n");
83 return -EINVAL;
84 }
85
86 if (header->header_version != BOOT_API_HEADER_VERSION) {
87 ERROR("Header version\n");
88 return -EINVAL;
89 }
90
91 for (i = 0U; i < header->image_length; i++) {
92 img_checksum += *(uint8_t *)(buffer + i);
93 }
94
95 if (header->payload_checksum != img_checksum) {
96 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
97 header->payload_checksum);
98 return -EINVAL;
99 }
100
101 return 0;
102}
Yann Gautiera55169b2020-01-10 18:18:59 +0100103
104int stm32mp_map_ddr_non_cacheable(void)
105{
106 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
107 STM32MP_DDR_MAX_SIZE,
108 MT_NON_CACHEABLE | MT_RW | MT_NS);
109}
110
111int stm32mp_unmap_ddr(void)
112{
113 return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
114 STM32MP_DDR_MAX_SIZE);
115}
Yann Gautiered6515d2021-03-08 15:03:35 +0100116
117/*****************************************************************************
118 * plat_is_smccc_feature_available() - This function checks whether SMCCC
119 * feature is availabile for platform.
120 * @fid: SMCCC function id
121 *
122 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
123 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
124 *****************************************************************************/
125int32_t plat_is_smccc_feature_available(u_register_t fid)
126{
127 switch (fid) {
128 case SMCCC_ARCH_SOC_ID:
129 return SMC_ARCH_CALL_SUCCESS;
130 default:
131 return SMC_ARCH_CALL_NOT_SUPPORTED;
132 }
133}
134
135/* Get SOC version */
136int32_t plat_get_soc_version(void)
137{
138 uint32_t chip_id = stm32mp_get_chip_dev_id();
139 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
140
141 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
142}
143
144/* Get SOC revision */
145int32_t plat_get_soc_revision(void)
146{
147 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
148}