Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <assert.h> |
| 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/debug.h> |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 13 | #include <drivers/st/stm32mp_clkfunc.h> |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 14 | #include <plat/common/platform.h> |
| 15 | |
| 16 | uintptr_t plat_get_ns_image_entrypoint(void) |
| 17 | { |
| 18 | return BL33_BASE; |
| 19 | } |
| 20 | |
| 21 | unsigned int plat_get_syscnt_freq2(void) |
| 22 | { |
| 23 | return read_cntfrq_el0(); |
| 24 | } |
| 25 | |
| 26 | static uintptr_t boot_ctx_address; |
| 27 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 28 | void stm32mp_save_boot_ctx_address(uintptr_t address) |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 29 | { |
| 30 | boot_ctx_address = address; |
| 31 | } |
| 32 | |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 33 | uintptr_t stm32mp_get_boot_ctx_address(void) |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 34 | { |
| 35 | return boot_ctx_address; |
| 36 | } |
| 37 | |
Yann Gautier | 3d78a2e | 2019-02-14 11:01:20 +0100 | [diff] [blame] | 38 | uintptr_t stm32mp_ddrctrl_base(void) |
| 39 | { |
| 40 | static uintptr_t ddrctrl_base; |
| 41 | |
| 42 | if (ddrctrl_base == 0) { |
| 43 | ddrctrl_base = dt_get_ddrctrl_base(); |
| 44 | |
| 45 | assert(ddrctrl_base == DDRCTRL_BASE); |
| 46 | } |
| 47 | |
| 48 | return ddrctrl_base; |
| 49 | } |
| 50 | |
| 51 | uintptr_t stm32mp_ddrphyc_base(void) |
| 52 | { |
| 53 | static uintptr_t ddrphyc_base; |
| 54 | |
| 55 | if (ddrphyc_base == 0) { |
| 56 | ddrphyc_base = dt_get_ddrphyc_base(); |
| 57 | |
| 58 | assert(ddrphyc_base == DDRPHYC_BASE); |
| 59 | } |
| 60 | |
| 61 | return ddrphyc_base; |
| 62 | } |
| 63 | |
| 64 | uintptr_t stm32mp_pwr_base(void) |
| 65 | { |
| 66 | static uintptr_t pwr_base; |
| 67 | |
| 68 | if (pwr_base == 0) { |
| 69 | pwr_base = dt_get_pwr_base(); |
| 70 | |
| 71 | assert(pwr_base == PWR_BASE); |
| 72 | } |
| 73 | |
| 74 | return pwr_base; |
| 75 | } |
| 76 | |
| 77 | uintptr_t stm32mp_rcc_base(void) |
| 78 | { |
| 79 | static uintptr_t rcc_base; |
| 80 | |
| 81 | if (rcc_base == 0) { |
| 82 | rcc_base = fdt_rcc_read_addr(); |
| 83 | |
| 84 | assert(rcc_base == RCC_BASE); |
| 85 | } |
| 86 | |
| 87 | return rcc_base; |
| 88 | } |
| 89 | |
Yann Gautier | f540a59 | 2019-05-22 19:13:51 +0200 | [diff] [blame^] | 90 | bool stm32mp_lock_available(void) |
| 91 | { |
| 92 | const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT; |
| 93 | |
| 94 | /* The spinlocks are used only when MMU and data cache are enabled */ |
| 95 | return (read_sctlr() & c_m_bits) == c_m_bits; |
| 96 | } |
| 97 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 98 | uintptr_t stm32_get_gpio_bank_base(unsigned int bank) |
| 99 | { |
| 100 | if (bank == GPIO_BANK_Z) { |
| 101 | return GPIOZ_BASE; |
| 102 | } |
| 103 | |
| 104 | assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); |
| 105 | |
| 106 | return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); |
| 107 | } |
| 108 | |
Yann Gautier | ee8f542 | 2019-02-14 11:13:25 +0100 | [diff] [blame] | 109 | uint32_t stm32_get_gpio_bank_offset(unsigned int bank) |
| 110 | { |
| 111 | if (bank == GPIO_BANK_Z) { |
| 112 | return 0; |
| 113 | } |
| 114 | |
| 115 | assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K); |
| 116 | |
| 117 | return bank * GPIO_BANK_OFFSET; |
| 118 | } |