| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 1 | /* |
| Bipin Ravi | 7f56547 | 2021-03-31 10:10:27 -0500 | [diff] [blame] | 2 | * Copyright (c) 2020-2021, Arm Limited. All rights reserved. |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_N2_H |
| 8 | #define NEOVERSE_N2_H |
| 9 | |
| 10 | /* Neoverse N2 ID register for revision r0p0 */ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 11 | #define NEOVERSE_N2_MIDR U(0x410FD490) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 12 | |
| 13 | /******************************************************************************* |
| 14 | * CPU Power control register |
| 15 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 16 | #define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 17 | #define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 18 | |
| 19 | /******************************************************************************* |
| 20 | * CPU Extended Control register specific definitions. |
| 21 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 22 | #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 |
| 23 | #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) |
| 24 | #define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 25 | |
| 26 | /******************************************************************************* |
| 27 | * CPU Auxiliary Control register specific definitions. |
| 28 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 29 | #define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 |
| 30 | #define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) |
| Bipin Ravi | eb35e85 | 2021-03-30 16:08:32 -0500 | [diff] [blame] | 31 | |
| 32 | /******************************************************************************* |
| 33 | * CPU Auxiliary Control register 2 specific definitions. |
| 34 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 35 | #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 |
| 36 | #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 37 | |
| Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 38 | /******************************************************************************* |
| 39 | * CPU Auxiliary Control register 5 specific definitions. |
| 40 | ******************************************************************************/ |
| nayanpatel-arm | d4c5f9c | 2021-09-28 09:46:45 -0700 | [diff] [blame] | 41 | #define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 |
| 42 | #define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * CPU Auxiliary Control register specific definitions. |
| 46 | ******************************************************************************/ |
| 47 | #define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 |
| 48 | #define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) |
| 49 | #define CPUECTLR2_EL1_PF_MODE_LSB U(11) |
| 50 | #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) |
| Bipin Ravi | 7e03069 | 2021-08-30 13:02:51 -0500 | [diff] [blame] | 51 | |
| Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 52 | #endif /* NEOVERSE_N2_H */ |