commit 7f5654772d2950a6af97283550c08a2c1ff82373
author Bipin Ravi <bipin.ravi@arm.com> Wed Mar 31 10:10:27 2021 -0500
committer Bipin Ravi <bipin.ravi@arm.com> Thu Sep 02 11:00:13 2021 -0500
tree 163376a7e9edf9fbadbc27c0512e849e51e45332
parent eb35e85c4bb6a8bc41dd8418bac20d00061bd356

errata: workaround for Neoverse N2 erratum 2025414

Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.

SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a

include/lib/cpus/aarch64/neoverse_n2.h

diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index a7211d2..68f6a40 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2021, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -21,6 +21,7 @@
  ******************************************************************************/
 #define NEOVERSE_N2_CPUECTLR_EL1		S3_0_C15_C1_4
 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT	(ULL(1) << 0)
+#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT	(ULL(1) << 8)
 
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.