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Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01001/*
2 * Copyright (c) 2020, Arm Limited. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_N2_H
8#define NEOVERSE_N2_H
9
10/* Neoverse N2 ID register for revision r0p0 */
11#define NEOVERSE_N2_MIDR U(0x410FD490)
12
13/*******************************************************************************
14 * CPU Power control register
15 ******************************************************************************/
16#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7
17#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0)
18
19/*******************************************************************************
20 * CPU Extended Control register specific definitions.
21 ******************************************************************************/
22#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4
23#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0)
24
25/*******************************************************************************
26 * CPU Auxiliary Control register specific definitions.
27 ******************************************************************************/
Bipin Ravieb35e852021-03-30 16:08:32 -050028#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0
29#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
30
31/*******************************************************************************
32 * CPU Auxiliary Control register 2 specific definitions.
33 ******************************************************************************/
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010034#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1
35#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
36
37#endif /* NEOVERSE_N2_H */