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Harry Liebelafd1ec72014-04-01 19:19:22 +01001/*
Dan Handley76076762015-03-19 19:26:52 +00002 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved.
Harry Liebelafd1ec72014-04-01 19:19:22 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <assert.h>
Dan Handley714a0d22014-04-09 13:13:04 +010032#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <mmio.h>
34#include <stddef.h>
35#include <tzc400.h>
Harry Liebelafd1ec72014-04-01 19:19:22 +010036
Dan Handley53c843a2014-08-04 19:53:05 +010037/*
38 * Implementation defined values used to validate inputs later.
39 * Filters : max of 4 ; 0 to 3
40 * Regions : max of 9 ; 0 to 8
41 * Address width : Values between 32 to 64
42 */
43typedef struct tzc_instance {
Juan Castillo7f1f0622014-09-09 09:49:23 +010044 uintptr_t base;
Dan Handley53c843a2014-08-04 19:53:05 +010045 uint8_t addr_width;
46 uint8_t num_filters;
47 uint8_t num_regions;
48} tzc_instance_t;
49
50tzc_instance_t tzc;
51
52
Juan Castillo7f1f0622014-09-09 09:49:23 +010053static inline uint32_t tzc_read_build_config(uintptr_t base)
Harry Liebelafd1ec72014-04-01 19:19:22 +010054{
55 return mmio_read_32(base + BUILD_CONFIG_OFF);
56}
57
Juan Castillo7f1f0622014-09-09 09:49:23 +010058static inline uint32_t tzc_read_gate_keeper(uintptr_t base)
Harry Liebelafd1ec72014-04-01 19:19:22 +010059{
60 return mmio_read_32(base + GATE_KEEPER_OFF);
61}
62
Juan Castillo7f1f0622014-09-09 09:49:23 +010063static inline void tzc_write_gate_keeper(uintptr_t base, uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +010064{
65 mmio_write_32(base + GATE_KEEPER_OFF, val);
66}
67
Juan Castillo7f1f0622014-09-09 09:49:23 +010068static inline void tzc_write_action(uintptr_t base, tzc_action_t action)
Harry Liebelafd1ec72014-04-01 19:19:22 +010069{
70 mmio_write_32(base + ACTION_OFF, action);
71}
72
Juan Castillo7f1f0622014-09-09 09:49:23 +010073static inline void tzc_write_region_base_low(uintptr_t base,
Dan Handley53c843a2014-08-04 19:53:05 +010074 uint32_t region,
75 uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +010076{
Dan Handley53c843a2014-08-04 19:53:05 +010077 mmio_write_32(base + REGION_BASE_LOW_OFF +
78 REGION_NUM_OFF(region), val);
Harry Liebelafd1ec72014-04-01 19:19:22 +010079}
80
Juan Castillo7f1f0622014-09-09 09:49:23 +010081static inline void tzc_write_region_base_high(uintptr_t base,
Dan Handley53c843a2014-08-04 19:53:05 +010082 uint32_t region,
83 uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +010084{
Dan Handley53c843a2014-08-04 19:53:05 +010085 mmio_write_32(base + REGION_BASE_HIGH_OFF +
86 REGION_NUM_OFF(region), val);
Harry Liebelafd1ec72014-04-01 19:19:22 +010087}
88
Juan Castillo7f1f0622014-09-09 09:49:23 +010089static inline void tzc_write_region_top_low(uintptr_t base,
Dan Handley53c843a2014-08-04 19:53:05 +010090 uint32_t region,
91 uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +010092{
Dan Handley53c843a2014-08-04 19:53:05 +010093 mmio_write_32(base + REGION_TOP_LOW_OFF +
94 REGION_NUM_OFF(region), val);
Harry Liebelafd1ec72014-04-01 19:19:22 +010095}
96
Juan Castillo7f1f0622014-09-09 09:49:23 +010097static inline void tzc_write_region_top_high(uintptr_t base,
Dan Handley53c843a2014-08-04 19:53:05 +010098 uint32_t region,
99 uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100100{
Dan Handley53c843a2014-08-04 19:53:05 +0100101 mmio_write_32(base + REGION_TOP_HIGH_OFF +
102 REGION_NUM_OFF(region), val);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100103}
104
Juan Castillo7f1f0622014-09-09 09:49:23 +0100105static inline void tzc_write_region_attributes(uintptr_t base,
Dan Handley53c843a2014-08-04 19:53:05 +0100106 uint32_t region,
107 uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100108{
Dan Handley53c843a2014-08-04 19:53:05 +0100109 mmio_write_32(base + REGION_ATTRIBUTES_OFF +
110 REGION_NUM_OFF(region), val);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100111}
112
Juan Castillo7f1f0622014-09-09 09:49:23 +0100113static inline void tzc_write_region_id_access(uintptr_t base,
Dan Handley53c843a2014-08-04 19:53:05 +0100114 uint32_t region,
115 uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100116{
Dan Handley53c843a2014-08-04 19:53:05 +0100117 mmio_write_32(base + REGION_ID_ACCESS_OFF +
118 REGION_NUM_OFF(region), val);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100119}
120
Juan Castillo7f1f0622014-09-09 09:49:23 +0100121static uint32_t tzc_read_component_id(uintptr_t base)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100122{
123 uint32_t id;
124
125 id = mmio_read_8(base + CID0_OFF);
126 id |= (mmio_read_8(base + CID1_OFF) << 8);
127 id |= (mmio_read_8(base + CID2_OFF) << 16);
128 id |= (mmio_read_8(base + CID3_OFF) << 24);
129
130 return id;
131}
132
Juan Castillo7f1f0622014-09-09 09:49:23 +0100133static uint32_t tzc_get_gate_keeper(uintptr_t base, uint8_t filter)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100134{
135 uint32_t tmp;
136
137 tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) &
138 GATE_KEEPER_OS_MASK;
139
Juan Castillof558cac2014-06-05 09:45:36 +0100140 return (tmp >> filter) & GATE_KEEPER_FILTER_MASK;
Harry Liebelafd1ec72014-04-01 19:19:22 +0100141}
142
143/* This function is not MP safe. */
Juan Castillo7f1f0622014-09-09 09:49:23 +0100144static void tzc_set_gate_keeper(uintptr_t base, uint8_t filter, uint32_t val)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100145{
146 uint32_t tmp;
147
148 /* Upper half is current state. Lower half is requested state. */
149 tmp = (tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) &
150 GATE_KEEPER_OS_MASK;
151
152 if (val)
153 tmp |= (1 << filter);
154 else
155 tmp &= ~(1 << filter);
156
157 tzc_write_gate_keeper(base, (tmp & GATE_KEEPER_OR_MASK) <<
158 GATE_KEEPER_OR_SHIFT);
159
160 /* Wait here until we see the change reflected in the TZC status. */
161 while (((tzc_read_gate_keeper(base) >> GATE_KEEPER_OS_SHIFT) &
162 GATE_KEEPER_OS_MASK) != tmp)
163 ;
164}
165
166
Juan Castillo7f1f0622014-09-09 09:49:23 +0100167void tzc_init(uintptr_t base)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100168{
169 uint32_t tzc_id, tzc_build;
170
Dan Handley53c843a2014-08-04 19:53:05 +0100171 assert(base);
172 tzc.base = base;
Harry Liebelafd1ec72014-04-01 19:19:22 +0100173
174 /*
175 * We expect to see a tzc400. Check component ID. The TZC-400 TRM shows
176 * component ID is expected to be "0xB105F00D".
177 */
Dan Handley53c843a2014-08-04 19:53:05 +0100178 tzc_id = tzc_read_component_id(tzc.base);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100179 if (tzc_id != TZC400_COMPONENT_ID) {
180 ERROR("TZC : Wrong device ID (0x%x).\n", tzc_id);
181 panic();
182 }
183
184 /* Save values we will use later. */
Dan Handley53c843a2014-08-04 19:53:05 +0100185 tzc_build = tzc_read_build_config(tzc.base);
186 tzc.num_filters = ((tzc_build >> BUILD_CONFIG_NF_SHIFT) &
Harry Liebelafd1ec72014-04-01 19:19:22 +0100187 BUILD_CONFIG_NF_MASK) + 1;
Dan Handley53c843a2014-08-04 19:53:05 +0100188 tzc.addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) &
Harry Liebelafd1ec72014-04-01 19:19:22 +0100189 BUILD_CONFIG_AW_MASK) + 1;
Dan Handley53c843a2014-08-04 19:53:05 +0100190 tzc.num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) &
Harry Liebelafd1ec72014-04-01 19:19:22 +0100191 BUILD_CONFIG_NR_MASK) + 1;
192}
193
Dan Handley76076762015-03-19 19:26:52 +0000194/*
195 * `tzc_configure_region0` is used to program region 0 into the TrustZone
196 * controller. Region 0 covers the whole address space that is not mapped
197 * to any other region, and is enabled on all filters; this cannot be
198 * changed. This function only changes the access permissions.
199 */
200void tzc_configure_region0(tzc_region_attributes_t sec_attr,
201 uint32_t ns_device_access)
202{
203 assert(tzc.base);
204
205 VERBOSE("TZC : Configuring region 0 (sec_attr=0x%x, ns_devs=0x%x)\n",
206 sec_attr, ns_device_access);
207
208 assert(sec_attr <= TZC_REGION_S_RDWR);
209
210 /* Set secure attributes on region 0 */
211 tzc_write_region_attributes(tzc.base, 0,
212 sec_attr << REG_ATTR_SEC_SHIFT);
213
214 /*
215 * Specify which non-secure devices have permission to access
216 * region 0.
217 */
218 tzc_write_region_id_access(tzc.base, 0, ns_device_access);
219}
220
Harry Liebelafd1ec72014-04-01 19:19:22 +0100221
222/*
223 * `tzc_configure_region` is used to program regions into the TrustZone
224 * controller. A region can be associated with more than one filter. The
225 * associated filters are passed in as a bitmap (bit0 = filter0).
226 * NOTE:
Dan Handley76076762015-03-19 19:26:52 +0000227 * Region 0 is special; it is preferable to use tzc_configure_region0
228 * for this region (see comment for that function).
Harry Liebelafd1ec72014-04-01 19:19:22 +0100229 */
Dan Handley53c843a2014-08-04 19:53:05 +0100230void tzc_configure_region(uint32_t filters,
Harry Liebelafd1ec72014-04-01 19:19:22 +0100231 uint8_t region,
232 uint64_t region_base,
233 uint64_t region_top,
Dan Handleye2712bc2014-04-10 15:37:22 +0100234 tzc_region_attributes_t sec_attr,
Harry Liebelafd1ec72014-04-01 19:19:22 +0100235 uint32_t ns_device_access)
236{
Dan Handley53c843a2014-08-04 19:53:05 +0100237 assert(tzc.base);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100238
Dan Handley76076762015-03-19 19:26:52 +0000239 VERBOSE("TZC : Configuring region (filters=0x%x, region=%d, ...\n",
240 filters, region);
241 VERBOSE("TZC : ... base=0x%lx, top=0x%lx, ...\n",
242 region_base, region_top);
243 VERBOSE("TZC : ... sec_attr=0x%x, ns_devs=0x%x)\n",
244 sec_attr, ns_device_access);
245
Harry Liebelafd1ec72014-04-01 19:19:22 +0100246 /* Do range checks on filters and regions. */
Dan Handley53c843a2014-08-04 19:53:05 +0100247 assert(((filters >> tzc.num_filters) == 0) &&
248 (region < tzc.num_regions));
Harry Liebelafd1ec72014-04-01 19:19:22 +0100249
250 /*
251 * Do address range check based on TZC configuration. A 64bit address is
252 * the max and expected case.
253 */
Dan Handley53c843a2014-08-04 19:53:05 +0100254 assert(((region_top <= (UINT64_MAX >> (64 - tzc.addr_width))) &&
255 (region_base < region_top)));
Harry Liebelafd1ec72014-04-01 19:19:22 +0100256
257 /* region_base and (region_top + 1) must be 4KB aligned */
258 assert(((region_base | (region_top + 1)) & (4096 - 1)) == 0);
259
260 assert(sec_attr <= TZC_REGION_S_RDWR);
261
262 /*
263 * Inputs look ok, start programming registers.
264 * All the address registers are 32 bits wide and have a LOW and HIGH
265 * component used to construct a up to a 64bit address.
266 */
Dan Handley53c843a2014-08-04 19:53:05 +0100267 tzc_write_region_base_low(tzc.base, region,
268 (uint32_t)(region_base));
269 tzc_write_region_base_high(tzc.base, region,
270 (uint32_t)(region_base >> 32));
Harry Liebelafd1ec72014-04-01 19:19:22 +0100271
Dan Handley53c843a2014-08-04 19:53:05 +0100272 tzc_write_region_top_low(tzc.base, region,
273 (uint32_t)(region_top));
274 tzc_write_region_top_high(tzc.base, region,
275 (uint32_t)(region_top >> 32));
Harry Liebelafd1ec72014-04-01 19:19:22 +0100276
277 /* Assign the region to a filter and set secure attributes */
Dan Handley53c843a2014-08-04 19:53:05 +0100278 tzc_write_region_attributes(tzc.base, region,
Juan Castillo921b8772014-09-05 17:29:38 +0100279 (sec_attr << REG_ATTR_SEC_SHIFT) | filters);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100280
281 /*
282 * Specify which non-secure devices have permission to access this
283 * region.
284 */
Dan Handley53c843a2014-08-04 19:53:05 +0100285 tzc_write_region_id_access(tzc.base, region, ns_device_access);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100286}
287
288
Dan Handley53c843a2014-08-04 19:53:05 +0100289void tzc_set_action(tzc_action_t action)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100290{
Dan Handley53c843a2014-08-04 19:53:05 +0100291 assert(tzc.base);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100292
293 /*
294 * - Currently no handler is provided to trap an error via interrupt
295 * or exception.
296 * - The interrupt action has not been tested.
297 */
Dan Handley53c843a2014-08-04 19:53:05 +0100298 tzc_write_action(tzc.base, action);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100299}
300
301
Dan Handley53c843a2014-08-04 19:53:05 +0100302void tzc_enable_filters(void)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100303{
304 uint32_t state;
305 uint32_t filter;
306
Dan Handley53c843a2014-08-04 19:53:05 +0100307 assert(tzc.base);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100308
Dan Handley53c843a2014-08-04 19:53:05 +0100309 for (filter = 0; filter < tzc.num_filters; filter++) {
310 state = tzc_get_gate_keeper(tzc.base, filter);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100311 if (state) {
Juan Castillof558cac2014-06-05 09:45:36 +0100312 /* The TZC filter is already configured. Changing the
313 * programmer's view in an active system can cause
314 * unpredictable behavior therefore panic for now rather
315 * than try to determine whether this is safe in this
316 * instance. See:
317 * http://infocenter.arm.com/help/index.jsp?\
318 * topic=/com.arm.doc.ddi0504c/CJHHECBF.html */
Harry Liebelafd1ec72014-04-01 19:19:22 +0100319 ERROR("TZC : Filter %d Gatekeeper already enabled.\n",
320 filter);
321 panic();
322 }
Dan Handley53c843a2014-08-04 19:53:05 +0100323 tzc_set_gate_keeper(tzc.base, filter, 1);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100324 }
325}
326
327
Dan Handley53c843a2014-08-04 19:53:05 +0100328void tzc_disable_filters(void)
Harry Liebelafd1ec72014-04-01 19:19:22 +0100329{
330 uint32_t filter;
331
Dan Handley53c843a2014-08-04 19:53:05 +0100332 assert(tzc.base);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100333
334 /*
335 * We don't do the same state check as above as the Gatekeepers are
336 * disabled after reset.
337 */
Dan Handley53c843a2014-08-04 19:53:05 +0100338 for (filter = 0; filter < tzc.num_filters; filter++)
339 tzc_set_gate_keeper(tzc.base, filter, 0);
Harry Liebelafd1ec72014-04-01 19:19:22 +0100340}