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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010034#include <auth_mod.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010035#include <bl1.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <bl_common.h>
Antonio Nino Diaze3962d02017-02-16 16:17:19 +000037#include <console.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010038#include <debug.h>
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +000039#include <errata_report.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010040#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010041#include <platform_def.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010042#include <smcc_helpers.h>
Soby Mathewc53ac5e2016-07-20 14:38:36 +010043#include <utils.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010044#include "bl1_private.h"
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010045#include <uuid.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010046
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010047/* BL1 Service UUID */
48DEFINE_SVC_UUID(bl1_svc_uid,
49 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
50 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
51
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052
Yatharth Kochara65be2f2015-10-09 18:06:13 +010053static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010054
Sandrine Bailleux467d0572014-06-24 14:02:34 +010055/*******************************************************************************
56 * The next function has a weak definition. Platform specific code can override
57 * it if it wishes to.
58 ******************************************************************************/
59#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010060
61/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010062 * Function that takes a memory layout into which BL2 has been loaded and
63 * populates a new memory layout for BL2 that ensures that BL1's data sections
64 * resident in secure RAM are not visible to BL2.
65 ******************************************************************************/
66void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
67 meminfo_t *bl2_mem_layout)
68{
Sandrine Bailleux467d0572014-06-24 14:02:34 +010069
70 assert(bl1_mem_layout != NULL);
71 assert(bl2_mem_layout != NULL);
72
Yatharth Kochar51f76f62016-09-12 16:10:33 +010073#if LOAD_IMAGE_V2
74 /*
75 * Remove BL1 RW data from the scope of memory visible to BL2.
76 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
77 */
78 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
79 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
80 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
81#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +010082 /* Check that BL1's memory is lying outside of the free memory */
83 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochara65be2f2015-10-09 18:06:13 +010084 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
85 bl1_mem_layout->free_size));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010086
87 /* Remove BL1 RW data from the scope of memory visible to BL2 */
88 *bl2_mem_layout = *bl1_mem_layout;
89 reserve_mem(&bl2_mem_layout->total_base,
90 &bl2_mem_layout->total_size,
91 BL1_RAM_BASE,
Yatharth Kochar51f76f62016-09-12 16:10:33 +010092 BL1_RAM_LIMIT - BL1_RAM_BASE);
93#endif /* LOAD_IMAGE_V2 */
Sandrine Bailleux467d0572014-06-24 14:02:34 +010094
95 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
96}
97
98/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100100 * It also queries the platform to load and run next BL image. Only called
101 * by the primary cpu after a cold boot.
102 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103void bl1_main(void)
104{
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100105 unsigned int image_id;
106
Dan Handley91b624e2014-07-29 17:14:00 +0100107 /* Announce our arrival */
108 NOTICE(FIRMWARE_WELCOME_STR);
109 NOTICE("BL1: %s\n", version_string);
110 NOTICE("BL1: %s\n", build_message);
111
Yatharth Kochar5d361212016-06-28 17:07:09 +0100112 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
113 (void *)BL1_RAM_LIMIT);
Dan Handley91b624e2014-07-29 17:14:00 +0100114
Jeenu Viswambharand5ec3672017-01-03 11:01:51 +0000115 print_errata_status();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000117#if ENABLE_ASSERTIONS
Yatharth Kochar5d361212016-06-28 17:07:09 +0100118 u_register_t val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100119 /*
120 * Ensure that MMU/Caches and coherency are turned on
121 */
Yatharth Kochar5d361212016-06-28 17:07:09 +0100122#ifdef AARCH32
123 val = read_sctlr();
124#else
Dan Handley0cdebbd2015-03-30 17:15:16 +0100125 val = read_sctlr_el3();
Yatharth Kochar5d361212016-06-28 17:07:09 +0100126#endif
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100127 assert(val & SCTLR_M_BIT);
128 assert(val & SCTLR_C_BIT);
129 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100130 /*
131 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
132 * provided platform value
133 */
134 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
135 /*
136 * If CWG is zero, then no CWG information is available but we can
137 * at least check the platform value is less than the architectural
138 * maximum.
139 */
140 if (val != 0)
141 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
142 else
143 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
Antonio Nino Diaz3759e3f2017-03-22 15:48:51 +0000144#endif /* ENABLE_ASSERTIONS */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145
146 /* Perform remaining generic architectural setup from EL3 */
147 bl1_arch_setup();
148
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100149#if TRUSTED_BOARD_BOOT
150 /* Initialize authentication module */
151 auth_mod_init();
152#endif /* TRUSTED_BOARD_BOOT */
153
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154 /* Perform platform setup in BL1. */
155 bl1_platform_setup();
156
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100157 /* Get the image id of next image to load and run. */
158 image_id = bl1_plat_get_next_image_id();
159
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100160 /*
161 * We currently interpret any image id other than
162 * BL2_IMAGE_ID as the start of firmware update.
163 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100164 if (image_id == BL2_IMAGE_ID)
165 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100166 else
167 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100168
169 bl1_prepare_next_image(image_id);
Antonio Nino Diaze3962d02017-02-16 16:17:19 +0000170
171 console_flush();
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100172}
173
174/*******************************************************************************
175 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
176 * Called by the primary cpu after a cold boot.
177 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
178 * loader etc.
179 ******************************************************************************/
180void bl1_load_bl2(void)
181{
182 image_desc_t *image_desc;
183 image_info_t *image_info;
184 entry_point_info_t *ep_info;
185 meminfo_t *bl1_tzram_layout;
186 meminfo_t *bl2_tzram_layout;
187 int err;
188
189 /* Get the image descriptor */
190 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
191 assert(image_desc);
192
193 /* Get the image info */
194 image_info = &image_desc->image_info;
195
196 /* Get the entry point info */
197 ep_info = &image_desc->ep_info;
Vikram Kanigirida567432014-04-15 18:08:08 +0100198
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100199 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000200 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100201
Juan Castillo3a66aca2015-04-13 17:36:19 +0100202 INFO("BL1: Loading BL2\n");
203
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100204#if LOAD_IMAGE_V2
205 err = load_auth_image(BL2_IMAGE_ID, image_info);
206#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100207 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100208 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100209 BL2_IMAGE_ID,
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100210 image_info->image_base,
211 image_info,
212 ep_info);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100213
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100214#endif /* LOAD_IMAGE_V2 */
215
Vikram Kanigirida567432014-04-15 18:08:08 +0100216 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100217 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100218 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100219 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000220
Achin Gupta4f6ad662013-10-25 09:08:21 +0100221 /*
222 * Create a new layout of memory for BL2 as seen by BL1 i.e.
223 * tell it the amount of total and free memory available.
224 * This layout is created at the first free address visible
225 * to BL2. BL2 will read the memory layout before using its
226 * memory for other purposes.
227 */
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100228#if LOAD_IMAGE_V2
229 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
230#else
Dan Handleye2712bc2014-04-10 15:37:22 +0100231 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100232#endif /* LOAD_IMAGE_V2 */
233
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100234 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235
Yatharth Kochar5d361212016-06-28 17:07:09 +0100236 ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100237 NOTICE("BL1: Booting BL2\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100238 VERBOSE("BL1: BL2 memory layout address = %p\n",
239 (void *) bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100240}
241
242/*******************************************************************************
Yatharth Kochar5d361212016-06-28 17:07:09 +0100243 * Function called just before handing over to the next BL to inform the user
244 * about the boot progress. In debug mode, also print details about the BL
245 * image's execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246 ******************************************************************************/
Yatharth Kochar5d361212016-06-28 17:07:09 +0100247void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248{
Yatharth Kochar5d361212016-06-28 17:07:09 +0100249#ifdef AARCH32
250 NOTICE("BL1: Booting BL32\n");
251#else
Juan Castillo7d199412015-12-14 09:35:25 +0000252 NOTICE("BL1: Booting BL31\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100253#endif /* AARCH32 */
254 print_entry_point_info(bl_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000256
257#if SPIN_ON_BL1_EXIT
258void print_debug_loop_message(void)
259{
260 NOTICE("BL1: Debug loop, spinning forever\n");
261 NOTICE("BL1: Please connect the debugger to continue\n");
262}
263#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100264
265/*******************************************************************************
266 * Top level handler for servicing BL1 SMCs.
267 ******************************************************************************/
268register_t bl1_smc_handler(unsigned int smc_fid,
269 register_t x1,
270 register_t x2,
271 register_t x3,
272 register_t x4,
273 void *cookie,
274 void *handle,
275 unsigned int flags)
276{
277
278#if TRUSTED_BOARD_BOOT
279 /*
280 * Dispatch FWU calls to FWU SMC handler and return its return
281 * value
282 */
283 if (is_fwu_fid(smc_fid)) {
284 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
285 handle, flags);
286 }
287#endif
288
289 switch (smc_fid) {
290 case BL1_SMC_CALL_COUNT:
291 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
292
293 case BL1_SMC_UID:
294 SMC_UUID_RET(handle, bl1_svc_uid);
295
296 case BL1_SMC_VERSION:
297 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
298
299 default:
300 break;
301 }
302
303 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
304 SMC_RET1(handle, SMC_UNK);
305}