Karl Li | eb62949 | 2023-04-27 14:00:10 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef APUSYS_RV_H |
| 8 | #define APUSYS_RV_H |
| 9 | |
| 10 | #include <platform_def.h> |
| 11 | |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 12 | #define APU_SEC_FW_IOVA (0x200000UL) |
| 13 | |
| 14 | /* APU_SCTRL_REVISER */ |
| 15 | #define UP_NORMAL_DOMAIN_NS (APU_REVISER + 0x0000) |
| 16 | #define UP_PRI_DOMAIN_NS (APU_REVISER + 0x0004) |
| 17 | #define UP_IOMMU_CTRL (APU_REVISER + 0x0008) |
| 18 | #define UP_CORE0_VABASE0 (APU_REVISER + 0x000c) |
| 19 | #define UP_CORE0_MVABASE0 (APU_REVISER + 0x0010) |
| 20 | #define UP_CORE0_VABASE1 (APU_REVISER + 0x0014) |
| 21 | #define UP_CORE0_MVABASE1 (APU_REVISER + 0x0018) |
Chungying Lu | ca30e6b | 2023-05-04 17:20:44 +0800 | [diff] [blame] | 22 | #define UP_CORE0_VABASE2 (APU_REVISER + 0x001c) |
| 23 | #define UP_CORE0_MVABASE2 (APU_REVISER + 0x0020) |
| 24 | #define UP_CORE0_VABASE3 (APU_REVISER + 0x0024) |
| 25 | #define UP_CORE0_MVABASE3 (APU_REVISER + 0x0028) |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 26 | #define USERFW_CTXT (APU_REVISER + 0x1000) |
| 27 | #define SECUREFW_CTXT (APU_REVISER + 0x1004) |
| 28 | #define UP_NORMAL_DOMAIN (7) |
| 29 | #define UP_NORMAL_NS (1) |
| 30 | #define UP_PRI_DOMAIN (5) |
| 31 | #define UP_PRI_NS (1) |
| 32 | #define UP_DOMAIN_SHIFT (0) |
| 33 | #define UP_NS_SHIFT (4) |
| 34 | #define MMU_EN BIT(0) |
| 35 | #define MMU_CTRL BIT(1) |
| 36 | #define MMU_CTRL_LOCK BIT(2) |
| 37 | #define VLD BIT(0) |
| 38 | #define PARTIAL_ENABLE BIT(1) |
| 39 | #define THREAD_NUM_PRI (1) |
| 40 | #define THREAD_NUM_NORMAL (0) |
| 41 | #define THREAD_NUM_SHIFT (2) |
| 42 | #define VASIZE_1MB BIT(0) |
| 43 | #define CFG_4GB_SEL_EN BIT(2) |
| 44 | #define CFG_4GB_SEL (0) |
| 45 | #define MVA_34BIT_SHIFT (2) |
| 46 | |
| 47 | /* APU_MD32_SYSCTRL */ |
| 48 | #define MD32_SYS_CTRL (APU_MD32_SYSCTRL + 0x0000) |
Chungying Lu | 4f3b5da | 2023-05-12 18:37:32 +0800 | [diff] [blame] | 49 | #define UP_INT_EN2 (APU_MD32_SYSCTRL + 0x000c) |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 50 | #define MD32_CLK_CTRL (APU_MD32_SYSCTRL + 0x00b8) |
| 51 | #define UP_WAKE_HOST_MASK0 (APU_MD32_SYSCTRL + 0x00bc) |
| 52 | #define UP_WAKE_HOST_MASK1 (APU_MD32_SYSCTRL + 0x00c0) |
| 53 | #define MD32_SYS_CTRL_RST (0) |
| 54 | #define MD32_G2B_CG_EN BIT(11) |
| 55 | #define MD32_DBG_EN BIT(10) |
| 56 | #define MD32_DM_AWUSER_IOMMU_EN BIT(9) |
| 57 | #define MD32_DM_ARUSER_IOMMU_EN BIT(7) |
| 58 | #define MD32_PM_AWUSER_IOMMU_EN BIT(5) |
| 59 | #define MD32_PM_ARUSER_IOMMU_EN BIT(3) |
| 60 | #define MD32_SOFT_RSTN BIT(0) |
| 61 | #define MD32_CLK_EN (1) |
Chungying Lu | 4f3b5da | 2023-05-12 18:37:32 +0800 | [diff] [blame] | 62 | #define MD32_CLK_DIS (0) |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 63 | #define WDT_IRQ_EN BIT(0) |
| 64 | #define MBOX0_IRQ_EN BIT(21) |
| 65 | #define MBOX1_IRQ_EN BIT(22) |
| 66 | #define MBOX2_IRQ_EN BIT(23) |
| 67 | #define RESET_DEALY_US (10) |
Chungying Lu | 4f3b5da | 2023-05-12 18:37:32 +0800 | [diff] [blame] | 68 | #define DBG_APB_EN BIT(31) |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 69 | |
| 70 | /* APU_AO_CTRL */ |
| 71 | #define MD32_PRE_DEFINE (APU_AO_CTRL + 0x0000) |
| 72 | #define MD32_BOOT_CTRL (APU_AO_CTRL + 0x0004) |
| 73 | #define MD32_RUNSTALL (APU_AO_CTRL + 0x0008) |
| 74 | #define PREDEFINE_NON_CACHE (0) |
| 75 | #define PREDEFINE_TCM (1) |
| 76 | #define PREDEFINE_CACHE (2) |
| 77 | #define PREDEFINE_CACHE_TCM (3) |
| 78 | #define PREDEF_1G_OFS (0) |
| 79 | #define PREDEF_2G_OFS (2) |
| 80 | #define PREDEF_3G_OFS (4) |
| 81 | #define PREDEF_4G_OFS (6) |
| 82 | #define MD32_RUN (0) |
| 83 | #define MD32_STALL (1) |
| 84 | |
| 85 | /* APU_MD32_WDT */ |
| 86 | #define WDT_INT (APU_MD32_WDT + 0x0) |
Chungying Lu | 4f3b5da | 2023-05-12 18:37:32 +0800 | [diff] [blame] | 87 | #define WDT_CTRL0 (APU_MD32_WDT + 0x4) |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 88 | #define WDT_INT_W1C (1) |
Chungying Lu | 4f3b5da | 2023-05-12 18:37:32 +0800 | [diff] [blame] | 89 | #define WDT_EN BIT(31) |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 90 | |
Karl Li | eb62949 | 2023-04-27 14:00:10 +0800 | [diff] [blame] | 91 | /* APU MBOX */ |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 92 | #define MBOX_FUNC_CFG (0xb0) |
| 93 | #define MBOX_DOMAIN_CFG (0xe0) |
| 94 | #define MBOX_CTRL_LOCK BIT(0) |
| 95 | #define MBOX_NO_MPU_SHIFT (16) |
| 96 | #define MBOX_RX_NS_SHIFT (16) |
| 97 | #define MBOX_RX_DOMAIN_SHIFT (17) |
| 98 | #define MBOX_TX_NS_SHIFT (24) |
| 99 | #define MBOX_TX_DOMAIN_SHIFT (25) |
| 100 | #define MBOX_SIZE (0x100) |
| 101 | #define MBOX_NUM (8) |
Karl Li | eb62949 | 2023-04-27 14:00:10 +0800 | [diff] [blame] | 102 | |
| 103 | #define APU_MBOX(i) (((i) < MBOX_NUM) ? (APU_MBOX0 + MBOX_SIZE * (i)) : \ |
| 104 | (APU_MBOX1 + MBOX_SIZE * ((i) - MBOX_NUM))) |
| 105 | #define APU_MBOX_FUNC_CFG(i) (APU_MBOX(i) + MBOX_FUNC_CFG) |
| 106 | #define APU_MBOX_DOMAIN_CFG(i) (APU_MBOX(i) + MBOX_DOMAIN_CFG) |
| 107 | |
| 108 | void apusys_rv_mbox_mpu_init(void); |
Chungying Lu | 15ffb07 | 2023-04-19 17:17:23 +0800 | [diff] [blame] | 109 | int apusys_kernel_apusys_rv_setup_reviser(void); |
| 110 | int apusys_kernel_apusys_rv_reset_mp(void); |
| 111 | int apusys_kernel_apusys_rv_setup_boot(void); |
| 112 | int apusys_kernel_apusys_rv_start_mp(void); |
| 113 | int apusys_kernel_apusys_rv_stop_mp(void); |
Chungying Lu | 59c1c2b | 2023-04-25 15:39:10 +0800 | [diff] [blame] | 114 | int apusys_kernel_apusys_rv_setup_sec_mem(void); |
Chungying Lu | 4f3b5da | 2023-05-12 18:37:32 +0800 | [diff] [blame] | 115 | int apusys_kernel_apusys_rv_disable_wdt_isr(void); |
| 116 | int apusys_kernel_apusys_rv_clear_wdt_isr(void); |
| 117 | int apusys_kernel_apusys_rv_cg_gating(void); |
| 118 | int apusys_kernel_apusys_rv_cg_ungating(void); |
Karl Li | eb62949 | 2023-04-27 14:00:10 +0800 | [diff] [blame] | 119 | |
| 120 | #endif /* APUSYS_RV_H */ |