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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Yatharth Kochar51f76f62016-09-12 16:10:33 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010034#include <auth_mod.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010035#include <bl1.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <bl_common.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010037#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010039#include <platform_def.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010040#include <smcc_helpers.h>
Soby Mathewc53ac5e2016-07-20 14:38:36 +010041#include <utils.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010042#include "bl1_private.h"
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010043#include <uuid.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010045/* BL1 Service UUID */
46DEFINE_SVC_UUID(bl1_svc_uid,
47 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
48 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
49
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010050
Yatharth Kochara65be2f2015-10-09 18:06:13 +010051static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052
Sandrine Bailleux467d0572014-06-24 14:02:34 +010053/*******************************************************************************
54 * The next function has a weak definition. Platform specific code can override
55 * it if it wishes to.
56 ******************************************************************************/
57#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010058
59/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010060 * Function that takes a memory layout into which BL2 has been loaded and
61 * populates a new memory layout for BL2 that ensures that BL1's data sections
62 * resident in secure RAM are not visible to BL2.
63 ******************************************************************************/
64void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
65 meminfo_t *bl2_mem_layout)
66{
Sandrine Bailleux467d0572014-06-24 14:02:34 +010067
68 assert(bl1_mem_layout != NULL);
69 assert(bl2_mem_layout != NULL);
70
Yatharth Kochar51f76f62016-09-12 16:10:33 +010071#if LOAD_IMAGE_V2
72 /*
73 * Remove BL1 RW data from the scope of memory visible to BL2.
74 * This is assuming BL1 RW data is at the top of bl1_mem_layout.
75 */
76 assert(BL1_RW_BASE > bl1_mem_layout->total_base);
77 bl2_mem_layout->total_base = bl1_mem_layout->total_base;
78 bl2_mem_layout->total_size = BL1_RW_BASE - bl1_mem_layout->total_base;
79#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +010080 /* Check that BL1's memory is lying outside of the free memory */
81 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochara65be2f2015-10-09 18:06:13 +010082 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
83 bl1_mem_layout->free_size));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010084
85 /* Remove BL1 RW data from the scope of memory visible to BL2 */
86 *bl2_mem_layout = *bl1_mem_layout;
87 reserve_mem(&bl2_mem_layout->total_base,
88 &bl2_mem_layout->total_size,
89 BL1_RAM_BASE,
Yatharth Kochar51f76f62016-09-12 16:10:33 +010090 BL1_RAM_LIMIT - BL1_RAM_BASE);
91#endif /* LOAD_IMAGE_V2 */
Sandrine Bailleux467d0572014-06-24 14:02:34 +010092
93 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
94}
95
96/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010098 * It also queries the platform to load and run next BL image. Only called
99 * by the primary cpu after a cold boot.
100 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100101void bl1_main(void)
102{
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100103 unsigned int image_id;
104
Dan Handley91b624e2014-07-29 17:14:00 +0100105 /* Announce our arrival */
106 NOTICE(FIRMWARE_WELCOME_STR);
107 NOTICE("BL1: %s\n", version_string);
108 NOTICE("BL1: %s\n", build_message);
109
Yatharth Kochar5d361212016-06-28 17:07:09 +0100110 INFO("BL1: RAM %p - %p\n", (void *)BL1_RAM_BASE,
111 (void *)BL1_RAM_LIMIT);
Dan Handley91b624e2014-07-29 17:14:00 +0100112
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113
Dan Handley0cdebbd2015-03-30 17:15:16 +0100114#if DEBUG
Yatharth Kochar5d361212016-06-28 17:07:09 +0100115 u_register_t val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116 /*
117 * Ensure that MMU/Caches and coherency are turned on
118 */
Yatharth Kochar5d361212016-06-28 17:07:09 +0100119#ifdef AARCH32
120 val = read_sctlr();
121#else
Dan Handley0cdebbd2015-03-30 17:15:16 +0100122 val = read_sctlr_el3();
Yatharth Kochar5d361212016-06-28 17:07:09 +0100123#endif
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100124 assert(val & SCTLR_M_BIT);
125 assert(val & SCTLR_C_BIT);
126 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100127 /*
128 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
129 * provided platform value
130 */
131 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
132 /*
133 * If CWG is zero, then no CWG information is available but we can
134 * at least check the platform value is less than the architectural
135 * maximum.
136 */
137 if (val != 0)
138 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
139 else
140 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
141#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100142
143 /* Perform remaining generic architectural setup from EL3 */
144 bl1_arch_setup();
145
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100146#if TRUSTED_BOARD_BOOT
147 /* Initialize authentication module */
148 auth_mod_init();
149#endif /* TRUSTED_BOARD_BOOT */
150
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151 /* Perform platform setup in BL1. */
152 bl1_platform_setup();
153
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100154 /* Get the image id of next image to load and run. */
155 image_id = bl1_plat_get_next_image_id();
156
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100157 /*
158 * We currently interpret any image id other than
159 * BL2_IMAGE_ID as the start of firmware update.
160 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100161 if (image_id == BL2_IMAGE_ID)
162 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100163 else
164 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100165
166 bl1_prepare_next_image(image_id);
167}
168
169/*******************************************************************************
170 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
171 * Called by the primary cpu after a cold boot.
172 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
173 * loader etc.
174 ******************************************************************************/
175void bl1_load_bl2(void)
176{
177 image_desc_t *image_desc;
178 image_info_t *image_info;
179 entry_point_info_t *ep_info;
180 meminfo_t *bl1_tzram_layout;
181 meminfo_t *bl2_tzram_layout;
182 int err;
183
184 /* Get the image descriptor */
185 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
186 assert(image_desc);
187
188 /* Get the image info */
189 image_info = &image_desc->image_info;
190
191 /* Get the entry point info */
192 ep_info = &image_desc->ep_info;
Vikram Kanigirida567432014-04-15 18:08:08 +0100193
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100194 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000195 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100196
Juan Castillo3a66aca2015-04-13 17:36:19 +0100197 INFO("BL1: Loading BL2\n");
198
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100199#if LOAD_IMAGE_V2
200 err = load_auth_image(BL2_IMAGE_ID, image_info);
201#else
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100202 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100203 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100204 BL2_IMAGE_ID,
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100205 image_info->image_base,
206 image_info,
207 ep_info);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100208
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100209#endif /* LOAD_IMAGE_V2 */
210
Vikram Kanigirida567432014-04-15 18:08:08 +0100211 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100212 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100213 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100214 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000215
Achin Gupta4f6ad662013-10-25 09:08:21 +0100216 /*
217 * Create a new layout of memory for BL2 as seen by BL1 i.e.
218 * tell it the amount of total and free memory available.
219 * This layout is created at the first free address visible
220 * to BL2. BL2 will read the memory layout before using its
221 * memory for other purposes.
222 */
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100223#if LOAD_IMAGE_V2
224 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base;
225#else
Dan Handleye2712bc2014-04-10 15:37:22 +0100226 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Yatharth Kochar51f76f62016-09-12 16:10:33 +0100227#endif /* LOAD_IMAGE_V2 */
228
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100229 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100230
Yatharth Kochar5d361212016-06-28 17:07:09 +0100231 ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout;
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100232 NOTICE("BL1: Booting BL2\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100233 VERBOSE("BL1: BL2 memory layout address = %p\n",
234 (void *) bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235}
236
237/*******************************************************************************
Yatharth Kochar5d361212016-06-28 17:07:09 +0100238 * Function called just before handing over to the next BL to inform the user
239 * about the boot progress. In debug mode, also print details about the BL
240 * image's execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241 ******************************************************************************/
Yatharth Kochar5d361212016-06-28 17:07:09 +0100242void bl1_print_next_bl_ep_info(const entry_point_info_t *bl_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100243{
Yatharth Kochar5d361212016-06-28 17:07:09 +0100244#ifdef AARCH32
245 NOTICE("BL1: Booting BL32\n");
246#else
Juan Castillo7d199412015-12-14 09:35:25 +0000247 NOTICE("BL1: Booting BL31\n");
Yatharth Kochar5d361212016-06-28 17:07:09 +0100248#endif /* AARCH32 */
249 print_entry_point_info(bl_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100250}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000251
252#if SPIN_ON_BL1_EXIT
253void print_debug_loop_message(void)
254{
255 NOTICE("BL1: Debug loop, spinning forever\n");
256 NOTICE("BL1: Please connect the debugger to continue\n");
257}
258#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100259
260/*******************************************************************************
261 * Top level handler for servicing BL1 SMCs.
262 ******************************************************************************/
263register_t bl1_smc_handler(unsigned int smc_fid,
264 register_t x1,
265 register_t x2,
266 register_t x3,
267 register_t x4,
268 void *cookie,
269 void *handle,
270 unsigned int flags)
271{
272
273#if TRUSTED_BOARD_BOOT
274 /*
275 * Dispatch FWU calls to FWU SMC handler and return its return
276 * value
277 */
278 if (is_fwu_fid(smc_fid)) {
279 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
280 handle, flags);
281 }
282#endif
283
284 switch (smc_fid) {
285 case BL1_SMC_CALL_COUNT:
286 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
287
288 case BL1_SMC_UID:
289 SMC_UUID_RET(handle, bl1_svc_uid);
290
291 case BL1_SMC_VERSION:
292 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
293
294 default:
295 break;
296 }
297
298 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
299 SMC_RET1(handle, SMC_UNK);
300}