blob: 399aebb05b857fd995415a150e9584e514e36c7b [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
Varun Wadekar4edc17c2017-11-20 17:14:47 -08002 * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bl31/bl31.h>
10#include <common/bl_common.h>
11#include <common/interrupt_props.h>
12#include <drivers/console.h>
13#include <context.h>
14#include <lib/el3_runtime/context_mgmt.h>
15#include <cortex_a57.h>
16#include <common/debug.h>
17#include <denver.h>
18#include <drivers/arm/gic_common.h>
19#include <drivers/arm/gicv2.h>
20#include <bl31/interrupt_mgmt.h>
21#include <mce.h>
Dilan Lee4e7a63c2017-08-10 16:01:42 +080022#include <mce_private.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070023#include <plat/common/platform.h>
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070024#include <spe.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070025#include <tegra_def.h>
Varun Wadekar128f46a2019-10-24 16:06:12 -070026#include <tegra_mc_def.h>
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070027#include <tegra_platform.h>
28#include <tegra_private.h>
29#include <lib/xlat_tables/xlat_tables_v2.h>
30
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070031/* ID for spe-console */
32#define TEGRA_CONSOLE_SPE_ID 0xFE
33
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070034/*******************************************************************************
35 * The Tegra power domain tree has a single system level power domain i.e. a
36 * single root node. The first entry in the power domain descriptor specifies
37 * the number of power domains at the highest power level.
38 *******************************************************************************
39 */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080040static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070041 /* No of root nodes */
42 1,
43 /* No of clusters */
44 PLATFORM_CLUSTER_COUNT,
45 /* No of CPU cores - cluster0 */
46 PLATFORM_MAX_CPUS_PER_CLUSTER,
47 /* No of CPU cores - cluster1 */
Varun Wadekara07d1c72017-08-23 14:59:09 -070048 PLATFORM_MAX_CPUS_PER_CLUSTER,
49 /* No of CPU cores - cluster2 */
50 PLATFORM_MAX_CPUS_PER_CLUSTER,
51 /* No of CPU cores - cluster3 */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070052 PLATFORM_MAX_CPUS_PER_CLUSTER
53};
54
Varun Wadekara7265be2017-04-28 08:45:53 -070055/*******************************************************************************
56 * This function returns the Tegra default topology tree information.
57 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080058const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekara7265be2017-04-28 08:45:53 -070059{
60 return tegra_power_domain_tree_desc;
61}
62
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070063/*
64 * Table of regions to map using the MMU.
65 */
66static const mmap_region_t tegra_mmap[] = {
Varun Wadekar03aa0142018-01-23 14:51:40 -080067 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080068 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
69 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
70 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar602cf7e2018-04-03 13:10:48 -070071 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
72 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080073 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080074 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080075 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080076 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070077#if !ENABLE_CONSOLE_SPE
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080078 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
79 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
80 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
81 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
82 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
83 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070084#endif
Varun Wadekar03aa0142018-01-23 14:51:40 -080085 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080086 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080087 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080088 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080089 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080090 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080091 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */
steven kaoe5796062018-01-02 19:09:04 -080092 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080093 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080094 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -080095 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x1000U, /* 4KB */
96 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
97 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +080098 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar9d15f7e2019-08-21 14:01:31 -070099#if ENABLE_CONSOLE_SPE
Varun Wadekar03aa0142018-01-23 14:51:40 -0800100 MAP_REGION_FLAT(TEGRA_CONSOLE_SPE_BASE, 0x1000U, /* 4KB */
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700101 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
102#endif
Varun Wadekar03aa0142018-01-23 14:51:40 -0800103 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, TEGRA_TMRUS_SIZE, /* 4KB */
steven kaoe5796062018-01-02 19:09:04 -0800104 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800105 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x1000U, /* 4KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800106 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800107 MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800108 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800109 MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800110 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800111 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x800000U, /* 8MB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800112 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800113 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, 0x10000U, /* 64KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800114 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekar03aa0142018-01-23 14:51:40 -0800115 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800116 (uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700117 {0}
118};
119
120/*******************************************************************************
121 * Set up the pagetables as per the platform memory map & initialize the MMU
122 ******************************************************************************/
123const mmap_region_t *plat_get_mmio_map(void)
124{
125 /* MMIO space */
126 return tegra_mmap;
127}
128
129/*******************************************************************************
130 * Handler to get the System Counter Frequency
131 ******************************************************************************/
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800132uint32_t plat_get_syscnt_freq2(void)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700133{
134 return 31250000;
135}
136
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700137#if !ENABLE_CONSOLE_SPE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700138/*******************************************************************************
139 * Maximum supported UART controllers
140 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800141#define TEGRA194_MAX_UART_PORTS 7
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700142
143/*******************************************************************************
144 * This variable holds the UART port base addresses
145 ******************************************************************************/
Varun Wadekar362a6b22017-11-10 11:04:42 -0800146static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700147 0, /* undefined - treated as an error case */
148 TEGRA_UARTA_BASE,
149 TEGRA_UARTB_BASE,
150 TEGRA_UARTC_BASE,
151 TEGRA_UARTD_BASE,
152 TEGRA_UARTE_BASE,
153 TEGRA_UARTF_BASE,
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800154 TEGRA_UARTG_BASE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700155};
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700156#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700157
158/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700159 * Enable console corresponding to the console ID
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700160 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700161void plat_enable_console(int32_t id)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700162{
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700163 uint32_t console_clock = 0U;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700164
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700165#if ENABLE_CONSOLE_SPE
Andre Przywaraabe890f2020-01-25 00:58:35 +0000166 static console_t spe_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700167
168 if (id == TEGRA_CONSOLE_SPE_ID) {
169 (void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
170 console_clock,
171 TEGRA_CONSOLE_BAUDRATE,
172 &spe_console);
Andre Przywara15069ea2020-01-25 00:58:35 +0000173 console_set_scope(&spe_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700174 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800175 }
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700176#else
Andre Przywara98b5a112020-01-25 00:58:35 +0000177 static console_t uart_console;
Anthony Zhou8bf6d4e2017-09-20 17:44:43 +0800178
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700179 if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
180 /*
181 * Reference clock used by the FPGAs is a lot slower.
182 */
183 if (tegra_platform_is_fpga()) {
184 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
185 } else {
186 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
187 }
188
189 (void)console_16550_register(tegra194_uart_addresses[id],
190 console_clock,
191 TEGRA_CONSOLE_BAUDRATE,
192 &uart_console);
Andre Przywara15069ea2020-01-25 00:58:35 +0000193 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700194 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
195 }
196#endif
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700197}
198
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700199/*******************************************************************************
200 * Handler for early platform setup
201 ******************************************************************************/
202void plat_early_platform_setup(void)
203{
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700204 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
205 uint8_t enable_ccplex_lock_step = params_from_bl2->enable_ccplex_lock_step;
206 uint64_t actlr_elx;
207
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700208 /* sanity check MCE firmware compatibility */
209 mce_verify_firmware_version();
210
David Pu70f65972019-03-18 15:14:49 -0700211#if RAS_EXTENSION
212 /* Enable Uncorrectable RAS error */
213 tegra194_ras_enable();
214#endif
215
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800216 /*
217 * Program XUSB STREAMIDs
218 * ======================
219 * T19x XUSB has support for XUSB virtualization. It will have one
Ajay Gupta81621092017-08-01 15:53:04 -0700220 * physical function (PF) and four Virtual function (VF)
221 *
222 * There were below two SIDs for XUSB until T186.
223 * 1) #define TEGRA_SID_XUSB_HOST 0x1bU
224 * 2) #define TEGRA_SID_XUSB_DEV 0x1cU
225 *
226 * We have below four new SIDs added for VF(s)
227 * 3) #define TEGRA_SID_XUSB_VF0 0x5dU
228 * 4) #define TEGRA_SID_XUSB_VF1 0x5eU
229 * 5) #define TEGRA_SID_XUSB_VF2 0x5fU
230 * 6) #define TEGRA_SID_XUSB_VF3 0x60U
231 *
232 * When virtualization is enabled then we have to disable SID override
233 * and program above SIDs in below newly added SID registers in XUSB
234 * PADCTL MMIO space. These registers are TZ protected and so need to
235 * be done in ATF.
236 * a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
237 * b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
238 * c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
239 * d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
240 * e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
241 * f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
242 *
243 * This change disables SID override and programs XUSB SIDs in
Varun Wadekar4edc17c2017-11-20 17:14:47 -0800244 * above registers to support both virtualization and
245 * non-virtualization platforms
Ajay Gupta81621092017-08-01 15:53:04 -0700246 */
Varun Wadekara2eb6632018-03-23 10:44:40 -0700247 if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
248
249 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
250 XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
251 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
252 XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
253 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
254 XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
255 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
256 XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
257 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
258 XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
259 mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
260 XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
261 }
Kalyani Chidambaramfcd1e882018-09-12 14:59:08 -0700262
263 /*
264 * Enable dual execution optimized translations for all ELx.
265 */
266 if (enable_ccplex_lock_step != 0U) {
267 actlr_elx = read_actlr_el3();
268 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL3;
269 write_actlr_el3(actlr_elx);
270
271 actlr_elx = read_actlr_el2();
272 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL2;
273 write_actlr_el2(actlr_elx);
274
275 actlr_elx = read_actlr_el1();
276 actlr_elx |= DENVER_CPU_ENABLE_DUAL_EXEC_EL1;
277 write_actlr_el1(actlr_elx);
278 }
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700279}
280
Varun Wadekar362a6b22017-11-10 11:04:42 -0800281/* Secure IRQs for Tegra194 */
282static const interrupt_prop_t tegra194_interrupt_props[] = {
Varun Wadekarbef02f02020-04-17 19:09:21 -0700283 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
284 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700285 INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar362a6b22017-11-10 11:04:42 -0800286 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700287 INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar362a6b22017-11-10 11:04:42 -0800288 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700289};
290
291/*******************************************************************************
292 * Initialize the GIC and SGIs
293 ******************************************************************************/
294void plat_gic_setup(void)
295{
Varun Wadekar362a6b22017-11-10 11:04:42 -0800296 tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
297 tegra_gic_init();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700298
299 /*
Varun Wadekar362a6b22017-11-10 11:04:42 -0800300 * Initialize the FIQ handler
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700301 */
Varun Wadekar362a6b22017-11-10 11:04:42 -0800302 tegra_fiq_handler_setup();
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700303}
304
305/*******************************************************************************
306 * Return pointer to the BL31 params from previous bootloader
307 ******************************************************************************/
308struct tegra_bl31_params *plat_get_bl31_params(void)
309{
Steven Kao08ac2732018-02-09 21:35:20 +0800310 uint64_t val;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700311
Steven Kao08ac2732018-02-09 21:35:20 +0800312 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_HI_ADDR) &
313 SCRATCH_BL31_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PARAMS_HI_ADDR_SHIFT;
314 val <<= 32;
315 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_LO_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700316
317 return (struct tegra_bl31_params *)(uintptr_t)val;
318}
319
320/*******************************************************************************
321 * Return pointer to the BL31 platform params from previous bootloader
322 ******************************************************************************/
323plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
324{
Steven Kao08ac2732018-02-09 21:35:20 +0800325 uint64_t val;
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700326
Steven Kao08ac2732018-02-09 21:35:20 +0800327 val = (mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_HI_ADDR) &
328 SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_MASK) >> SCRATCH_BL31_PLAT_PARAMS_HI_ADDR_SHIFT;
329 val <<= 32;
330 val |= mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_LO_ADDR);
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700331
332 return (plat_params_from_bl2_t *)(uintptr_t)val;
333}
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800334
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700335/*******************************************************************************
336 * Handler for late platform setup
337 ******************************************************************************/
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800338void plat_late_platform_setup(void)
339{
Steven Kao8f4f1022017-12-13 06:39:15 +0800340#if ENABLE_STRICT_CHECKING_MODE
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800341 /*
342 * Enable strict checking after programming the GSC for
343 * enabling TZSRAM and TZDRAM
344 */
345 mce_enable_strict_checking();
Steven Kao8f4f1022017-12-13 06:39:15 +0800346#endif
Dilan Lee4e7a63c2017-08-10 16:01:42 +0800347}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700348
349/*******************************************************************************
350 * Handler to indicate support for System Suspend
351 ******************************************************************************/
352bool plat_supports_system_suspend(void)
353{
354 return true;
355}