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git01.mediatek.com / filogic / atf / 7a554a1344212fb5068b764fdb010d7fc2c73f47 / . / include / plat / arm / board / common / board_css_def.h
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Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
Suyash Pathak00b99832020-02-12 10:36:20 +0530[diff] [blame]2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef BOARD_CSS_DEF_H
8#define BOARD_CSS_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +0000[diff] [blame]11#include <plat/arm/board/common/v2m_def.h>
12#include <plat/arm/soc/common/soc_css_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]13#include <plat/common/common_def.h>
14
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]15/*
16 * Definitions common to all ARM CSS-based development platforms
17 */
18
19/* Platform ID address */
20#define BOARD_CSS_PLAT_ID_REG_ADDR 0x7ffe00e0
21
22/* Platform ID related accessors */
23#define BOARD_CSS_PLAT_ID_REG_ID_MASK 0x0f
24#define BOARD_CSS_PLAT_ID_REG_ID_SHIFT 0x0
25#define BOARD_CSS_PLAT_ID_REG_VERSION_MASK 0xf00
26#define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT 0x8
27#define BOARD_CSS_PLAT_TYPE_RTL 0x00
28#define BOARD_CSS_PLAT_TYPE_FPGA 0x01
29#define BOARD_CSS_PLAT_TYPE_EMULATOR 0x02
30#define BOARD_CSS_PLAT_TYPE_FVP 0x03
31
Julius Werner53456fc2019-07-09 13:49:11 -0700[diff] [blame]32#ifndef __ASSEMBLER__
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]33
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]34#include <lib/mmio.h>
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]35
36#define BOARD_CSS_GET_PLAT_TYPE(addr) \
37 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \
38 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT)
39
Julius Werner53456fc2019-07-09 13:49:11 -0700[diff] [blame]40#endif /* __ASSEMBLER__ */
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]41
42
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100[diff] [blame]43#define MAX_IO_DEVICES 3
44#define MAX_IO_HANDLES 4
45
46/* Reserve the last block of flash for PSCI MEM PROTECT flag */
47#define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE
48#define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
49
50#define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE
51#define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
52
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]53/* UART related constants */
54#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE
55#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ
56
Usama Arif81eb5ce2019-02-11 16:35:42 +0000[diff] [blame]57#define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE
58#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
Soby Mathew2fd66be2015-12-09 11:38:43 +0000[diff] [blame]59
Dimitris Papastamos52323b02017-06-07 13:45:41 +0100[diff] [blame]60#define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE
61#define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ
62
Usama Arif81eb5ce2019-02-11 16:35:42 +0000[diff] [blame]63#define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE
64#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]65
66#define PLAT_ARM_TSP_UART_BASE V2M_IOFPGA_UART0_BASE
67#define PLAT_ARM_TSP_UART_CLK_IN_HZ V2M_IOFPGA_UART0_CLK_IN_HZ
68
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]69#endif /* BOARD_CSS_DEF_H */