| Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 1 | # Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. |
| 2 | # |
| 3 | # SPDX-License-Identifier: BSD-3-Clause |
| 4 | # |
| 5 | |
| 6 | CSS_LOAD_SCP_IMAGES := 1 |
| 7 | |
| 8 | CSS_USE_SCMI_SDS_DRIVER := 1 |
| 9 | |
| 10 | RAS_EXTENSION := 0 |
| 11 | |
| 12 | SDEI_SUPPORT := 0 |
| 13 | |
| 14 | EL3_EXCEPTION_HANDLING := 0 |
| 15 | |
| 16 | HANDLE_EA_EL3_FIRST := 0 |
| 17 | |
| 18 | # System coherency is managed in hardware |
| 19 | HW_ASSISTED_COHERENCY := 1 |
| 20 | |
| 21 | # When building for systems with hardware-assisted coherency, there's no need to |
| 22 | # use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too. |
| 23 | USE_COHERENT_MEM := 0 |
| 24 | |
| 25 | GIC_ENABLE_V4_EXTN := 1 |
| 26 | |
| 27 | # GIC-600 configuration |
| Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 28 | GICV3_SUPPORT_GIC600 := 1 |
| 29 | |
| Usama Arif | bec5afd | 2020-04-17 16:13:39 +0100 | [diff] [blame] | 30 | |
| 31 | # Include GICv3 driver files |
| 32 | include drivers/arm/gic/v3/gicv3.mk |
| 33 | |
| 34 | ENT_GIC_SOURCES := ${GICV3_SOURCES} \ |
| 35 | plat/common/plat_gicv3.c \ |
| 36 | plat/arm/common/arm_gicv3.c |
| 37 | |
| 38 | override NEED_BL2U := no |
| 39 | |
| 40 | override ARM_PLAT_MT := 1 |
| 41 | |
| 42 | TC0_BASE = plat/arm/board/tc0 |
| 43 | |
| 44 | PLAT_INCLUDES += -I${TC0_BASE}/include/ |
| 45 | |
| 46 | TC0_CPU_SOURCES := lib/cpus/aarch64/cortex_matterhorn.S |
| 47 | |
| 48 | INTERCONNECT_SOURCES := ${TC0_BASE}/tc0_interconnect.c |
| 49 | |
| 50 | PLAT_BL_COMMON_SOURCES += ${TC0_BASE}/tc0_plat.c \ |
| 51 | ${TC0_BASE}/include/tc0_helpers.S |
| 52 | |
| 53 | BL1_SOURCES += ${INTERCONNECT_SOURCES} \ |
| 54 | ${TC0_CPU_SOURCES} \ |
| 55 | ${TC0_BASE}/tc0_trusted_boot.c \ |
| 56 | ${TC0_BASE}/tc0_err.c \ |
| 57 | drivers/arm/sbsa/sbsa.c |
| 58 | |
| 59 | |
| 60 | BL2_SOURCES += ${TC0_BASE}/tc0_security.c \ |
| 61 | ${TC0_BASE}/tc0_err.c \ |
| 62 | ${TC0_BASE}/tc0_trusted_boot.c \ |
| 63 | lib/utils/mem_region.c \ |
| 64 | plat/arm/common/arm_nor_psci_mem_protect.c |
| 65 | |
| 66 | BL31_SOURCES += ${INTERCONNECT_SOURCES} \ |
| 67 | ${TC0_CPU_SOURCES} \ |
| 68 | ${ENT_GIC_SOURCES} \ |
| 69 | ${TC0_BASE}/tc0_bl31_setup.c \ |
| 70 | ${TC0_BASE}/tc0_topology.c \ |
| 71 | drivers/cfi/v2m/v2m_flash.c \ |
| 72 | lib/utils/mem_region.c \ |
| 73 | plat/arm/common/arm_nor_psci_mem_protect.c |
| 74 | |
| 75 | # Add the FDT_SOURCES and options for Dynamic Config |
| 76 | FDT_SOURCES += ${TC0_BASE}/fdts/${PLAT}_fw_config.dts |
| 77 | TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb |
| 78 | |
| 79 | # Add the TB_FW_CONFIG to FIP and specify the same to certtool |
| 80 | $(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config)) |
| 81 | |
| 82 | #Device tree |
| 83 | TC0_HW_CONFIG_DTS := fdts/tc0.dts |
| 84 | TC0_HW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}.dtb |
| 85 | FDT_SOURCES += ${TC0_HW_CONFIG_DTS} |
| 86 | $(eval TC0_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(TC0_HW_CONFIG_DTS))) |
| 87 | |
| 88 | # Add the HW_CONFIG to FIP and specify the same to certtool |
| 89 | $(eval $(call TOOL_ADD_PAYLOAD,${TC0_HW_CONFIG},--hw-config)) |
| 90 | |
| 91 | override CTX_INCLUDE_AARCH32_REGS := 0 |
| 92 | |
| 93 | override CTX_INCLUDE_PAUTH_REGS := 1 |
| 94 | |
| 95 | include plat/arm/common/arm_common.mk |
| 96 | include plat/arm/css/common/css_common.mk |
| 97 | include plat/arm/soc/common/soc_css.mk |
| 98 | include plat/arm/board/common/board_common.mk |