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git01.mediatek.com / filogic / atf / 78a6e0c46ae6031867f16f666eaa3eefa1b8286e / . / plat / fvp / bl32_plat_setup.c
blob: ba418fdd0a75d71ec8d2b24a109f7b4f67870dcd [file] [log] [blame]
Achin Gupta7c88f3f2014-02-18 18:09:12 +0000[diff] [blame]1/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <string.h>
32#include <assert.h>
33#include <arch_helpers.h>
34#include <platform.h>
35#include <bl32.h>
36#include <bl_common.h>
37#include <console.h>
38
39/*******************************************************************************
40 * Declarations of linker defined symbols which will help us find the layout
41 * of trusted SRAM
42 ******************************************************************************/
43extern unsigned long __RO_START__;
44extern unsigned long __RO_END__;
45
46extern unsigned long __COHERENT_RAM_START__;
47extern unsigned long __COHERENT_RAM_END__;
48
49/*
50 * The next 2 constants identify the extents of the code & RO data region.
51 * These addresses are used by the MMU setup code and therefore they must be
52 * page-aligned. It is the responsibility of the linker script to ensure that
53 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
54 */
55#define BL32_RO_BASE (unsigned long)(&__RO_START__)
56#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
57
58/*
59 * The next 2 constants identify the extents of the coherent memory region.
60 * These addresses are used by the MMU setup code and therefore they must be
61 * page-aligned. It is the responsibility of the linker script to ensure that
62 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
63 * page-aligned addresses.
64 */
65#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
66#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
67
68/* Data structure which holds the extents of the trusted SRAM for BL32 */
69static meminfo bl32_tzdram_layout
70__attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
71 section("tzfw_coherent_mem")));
72
73meminfo *bl32_plat_sec_mem_layout(void)
74{
75 return &bl32_tzdram_layout;
76}
77
78/*******************************************************************************
79 * BL1 has passed the extents of the trusted SRAM that's at BL32's disposal.
80 * Initialize the BL32 data structure with the memory extends
81 ******************************************************************************/
82void bl32_early_platform_setup(meminfo *mem_layout,
83 void *data)
84{
85 /* Setup the BL32 memory layout */
86 bl32_tzdram_layout.total_base = mem_layout->total_base;
87 bl32_tzdram_layout.total_size = mem_layout->total_size;
88 bl32_tzdram_layout.free_base = mem_layout->free_base;
89 bl32_tzdram_layout.free_size = mem_layout->free_size;
90 bl32_tzdram_layout.attr = mem_layout->attr;
91 bl32_tzdram_layout.next = 0;
92
93 return;
94}
95
96/*******************************************************************************
97 * Perform platform specific setup
98 ******************************************************************************/
99void bl32_platform_setup()
100{
101 /*
102 * Initialize a different console than already in use to display
103 * messages from TSP
104 */
105 console_init(PL011_UART1_BASE);
106}
107
108/*******************************************************************************
109 * Perform the very early platform specific architectural setup here. At the
110 * moment this is only intializes the MMU
111 ******************************************************************************/
112void bl32_plat_arch_setup()
113{
114 configure_mmu(&bl32_tzdram_layout,
115 BL32_RO_BASE,
116 BL32_RO_LIMIT,
117 BL32_COHERENT_RAM_BASE,
118 BL32_COHERENT_RAM_LIMIT);
119}