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Yann Gautieree8f5422019-02-14 11:13:25 +01001/*
Yann Gautierd0714c02022-01-05 18:02:46 +01002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Yann Gautieree8f5422019-02-14 11:13:25 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
Yann Gautiere97b6632019-04-19 10:48:36 +02008#include <errno.h>
Yann Gautieree8f5422019-02-14 11:13:25 +01009
Yann Gautieree8f5422019-02-14 11:13:25 +010010#include <arch_helpers.h>
11#include <common/debug.h>
Yann Gautiera205a5c2021-08-30 15:06:54 +020012#include <drivers/clk.h>
Yann Gautier7a819122021-10-18 15:26:33 +020013#include <drivers/delay_timer.h>
14#include <drivers/st/stm32_console.h>
Yann Gautier3d78a2e2019-02-14 11:01:20 +010015#include <drivers/st/stm32mp_clkfunc.h>
Yann Gautier7a819122021-10-18 15:26:33 +020016#include <drivers/st/stm32mp_reset.h>
Yann Gautiered6515d2021-03-08 15:03:35 +010017#include <lib/smccc.h>
Yann Gautiera55169b2020-01-10 18:18:59 +010018#include <lib/xlat_tables/xlat_tables_v2.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010019#include <plat/common/platform.h>
Yann Gautiered6515d2021-03-08 15:03:35 +010020#include <services/arm_arch_svc.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010021
Yann Gautier7a819122021-10-18 15:26:33 +020022#include <platform_def.h>
23
Nicolas Le Bayondc4bcba2019-11-18 17:12:27 +010024#define HEADER_VERSION_MAJOR_MASK GENMASK(23, 16)
Yann Gautier7a819122021-10-18 15:26:33 +020025#define RESET_TIMEOUT_US_1MS 1000U
26
27static console_t console;
Nicolas Le Bayondc4bcba2019-11-18 17:12:27 +010028
Yann Gautieree8f5422019-02-14 11:13:25 +010029uintptr_t plat_get_ns_image_entrypoint(void)
30{
31 return BL33_BASE;
32}
33
34unsigned int plat_get_syscnt_freq2(void)
35{
36 return read_cntfrq_el0();
37}
38
39static uintptr_t boot_ctx_address;
Yann Gautiercf1360d2020-08-27 18:28:57 +020040static uint16_t boot_itf_selected;
Yann Gautieree8f5422019-02-14 11:13:25 +010041
Yann Gautiera2e2a302019-02-14 11:13:39 +010042void stm32mp_save_boot_ctx_address(uintptr_t address)
Yann Gautieree8f5422019-02-14 11:13:25 +010043{
Yann Gautiercf1360d2020-08-27 18:28:57 +020044 boot_api_context_t *boot_context = (boot_api_context_t *)address;
45
Yann Gautieree8f5422019-02-14 11:13:25 +010046 boot_ctx_address = address;
Yann Gautiercf1360d2020-08-27 18:28:57 +020047 boot_itf_selected = boot_context->boot_interface_selected;
Yann Gautieree8f5422019-02-14 11:13:25 +010048}
49
Yann Gautiera2e2a302019-02-14 11:13:39 +010050uintptr_t stm32mp_get_boot_ctx_address(void)
Yann Gautieree8f5422019-02-14 11:13:25 +010051{
52 return boot_ctx_address;
53}
54
Yann Gautiercf1360d2020-08-27 18:28:57 +020055uint16_t stm32mp_get_boot_itf_selected(void)
56{
57 return boot_itf_selected;
58}
59
Yann Gautier3d78a2e2019-02-14 11:01:20 +010060uintptr_t stm32mp_ddrctrl_base(void)
61{
Yann Gautiera18f61b2020-05-05 17:58:40 +020062 return DDRCTRL_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010063}
64
65uintptr_t stm32mp_ddrphyc_base(void)
66{
Yann Gautiera18f61b2020-05-05 17:58:40 +020067 return DDRPHYC_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010068}
69
70uintptr_t stm32mp_pwr_base(void)
71{
Yann Gautiera18f61b2020-05-05 17:58:40 +020072 return PWR_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010073}
74
75uintptr_t stm32mp_rcc_base(void)
76{
Yann Gautiera18f61b2020-05-05 17:58:40 +020077 return RCC_BASE;
Yann Gautier3d78a2e2019-02-14 11:01:20 +010078}
79
Yann Gautierf540a592019-05-22 19:13:51 +020080bool stm32mp_lock_available(void)
81{
82 const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
83
84 /* The spinlocks are used only when MMU and data cache are enabled */
85 return (read_sctlr() & c_m_bits) == c_m_bits;
86}
87
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020088#if STM32MP_USE_STM32IMAGE
Yann Gautiere97b6632019-04-19 10:48:36 +020089int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
90{
91 uint32_t i;
92 uint32_t img_checksum = 0U;
93
94 /*
95 * Check header/payload validity:
96 * - Header magic
97 * - Header version
98 * - Payload checksum
99 */
100 if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
101 ERROR("Header magic\n");
102 return -EINVAL;
103 }
104
Nicolas Le Bayondc4bcba2019-11-18 17:12:27 +0100105 if ((header->header_version & HEADER_VERSION_MAJOR_MASK) !=
106 (BOOT_API_HEADER_VERSION & HEADER_VERSION_MAJOR_MASK)) {
Yann Gautiere97b6632019-04-19 10:48:36 +0200107 ERROR("Header version\n");
108 return -EINVAL;
109 }
110
111 for (i = 0U; i < header->image_length; i++) {
112 img_checksum += *(uint8_t *)(buffer + i);
113 }
114
115 if (header->payload_checksum != img_checksum) {
116 ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
117 header->payload_checksum);
118 return -EINVAL;
119 }
120
121 return 0;
122}
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200123#endif /* STM32MP_USE_STM32IMAGE */
Yann Gautiera55169b2020-01-10 18:18:59 +0100124
125int stm32mp_map_ddr_non_cacheable(void)
126{
127 return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
128 STM32MP_DDR_MAX_SIZE,
Yann Gautierf3bd87e2020-09-04 15:55:53 +0200129 MT_NON_CACHEABLE | MT_RW | MT_SECURE);
Yann Gautiera55169b2020-01-10 18:18:59 +0100130}
131
132int stm32mp_unmap_ddr(void)
133{
134 return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
135 STM32MP_DDR_MAX_SIZE);
136}
Yann Gautiered6515d2021-03-08 15:03:35 +0100137
Lionel Debievebc2d88d2019-11-04 14:31:38 +0100138int stm32_get_otp_index(const char *otp_name, uint32_t *otp_idx,
139 uint32_t *otp_len)
140{
141 assert(otp_name != NULL);
142 assert(otp_idx != NULL);
143
144 return dt_find_otp_name(otp_name, otp_idx, otp_len);
145}
146
147int stm32_get_otp_value(const char *otp_name, uint32_t *otp_val)
148{
149 uint32_t otp_idx;
150
151 assert(otp_name != NULL);
152 assert(otp_val != NULL);
153
154 if (stm32_get_otp_index(otp_name, &otp_idx, NULL) != 0) {
155 return -1;
156 }
157
158 if (stm32_get_otp_value_from_idx(otp_idx, otp_val) != 0) {
159 ERROR("BSEC: %s Read Error\n", otp_name);
160 return -1;
161 }
162
163 return 0;
164}
165
166int stm32_get_otp_value_from_idx(const uint32_t otp_idx, uint32_t *otp_val)
167{
168 uint32_t ret = BSEC_NOT_SUPPORTED;
169
170 assert(otp_val != NULL);
171
172#if defined(IMAGE_BL2)
173 ret = bsec_shadow_read_otp(otp_val, otp_idx);
174#elif defined(IMAGE_BL32)
175 ret = bsec_read_otp(otp_val, otp_idx);
176#else
177#error "Not supported"
178#endif
179 if (ret != BSEC_OK) {
180 ERROR("BSEC: idx=%u Read Error\n", otp_idx);
181 return -1;
182 }
183
184 return 0;
185}
186
Yann Gautier414f17c2021-10-18 15:50:05 +0200187#if defined(IMAGE_BL2)
Yann Gautier7a819122021-10-18 15:26:33 +0200188static void reset_uart(uint32_t reset)
189{
190 int ret;
191
192 ret = stm32mp_reset_assert(reset, RESET_TIMEOUT_US_1MS);
193 if (ret != 0) {
194 panic();
195 }
196
197 udelay(2);
198
199 ret = stm32mp_reset_deassert(reset, RESET_TIMEOUT_US_1MS);
200 if (ret != 0) {
201 panic();
202 }
203
204 mdelay(1);
205}
Yann Gautier414f17c2021-10-18 15:50:05 +0200206#endif
Yann Gautier7a819122021-10-18 15:26:33 +0200207
Yann Gautierd1435742021-10-18 10:55:23 +0200208static void set_console(uintptr_t base, uint32_t clk_rate)
209{
210 unsigned int console_flags;
211
212 if (console_stm32_register(base, clk_rate,
Yann Gautierb02dd492022-03-02 14:31:55 +0100213 (uint32_t)STM32MP_UART_BAUDRATE, &console) == 0) {
Yann Gautierd1435742021-10-18 10:55:23 +0200214 panic();
215 }
216
217 console_flags = CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH |
218 CONSOLE_FLAG_TRANSLATE_CRLF;
219#if !defined(IMAGE_BL2) && defined(DEBUG)
220 console_flags |= CONSOLE_FLAG_RUNTIME;
221#endif
222
223 console_set_scope(&console, console_flags);
224}
225
Yann Gautier7a819122021-10-18 15:26:33 +0200226int stm32mp_uart_console_setup(void)
227{
228 struct dt_node_info dt_uart_info;
Yann Gautierd0714c02022-01-05 18:02:46 +0100229 uint32_t clk_rate = 0U;
Yann Gautier7a819122021-10-18 15:26:33 +0200230 int result;
Yann Gautier3d8497c2021-10-18 16:06:22 +0200231 uint32_t boot_itf __unused;
232 uint32_t boot_instance __unused;
Yann Gautier7a819122021-10-18 15:26:33 +0200233
234 result = dt_get_stdout_uart_info(&dt_uart_info);
235
236 if ((result <= 0) ||
Yann Gautierd0714c02022-01-05 18:02:46 +0100237 (dt_uart_info.status == DT_DISABLED)) {
238 return -ENODEV;
239 }
240
241#if defined(IMAGE_BL2)
242 if ((dt_uart_info.clock < 0) ||
Yann Gautier7a819122021-10-18 15:26:33 +0200243 (dt_uart_info.reset < 0)) {
244 return -ENODEV;
245 }
Yann Gautierd0714c02022-01-05 18:02:46 +0100246#endif
Yann Gautier7a819122021-10-18 15:26:33 +0200247
Yann Gautier3d8497c2021-10-18 16:06:22 +0200248#if STM32MP_UART_PROGRAMMER || !defined(IMAGE_BL2)
249 stm32_get_boot_interface(&boot_itf, &boot_instance);
250
251 if ((boot_itf == BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) &&
252 (get_uart_address(boot_instance) == dt_uart_info.base)) {
253 return -EACCES;
254 }
255#endif
256
Yann Gautier414f17c2021-10-18 15:50:05 +0200257#if defined(IMAGE_BL2)
Yann Gautier7a819122021-10-18 15:26:33 +0200258 if (dt_set_stdout_pinctrl() != 0) {
259 return -ENODEV;
260 }
261
Yann Gautiera205a5c2021-08-30 15:06:54 +0200262 clk_enable((unsigned long)dt_uart_info.clock);
Yann Gautier7a819122021-10-18 15:26:33 +0200263
264 reset_uart((uint32_t)dt_uart_info.reset);
265
Yann Gautiera205a5c2021-08-30 15:06:54 +0200266 clk_rate = clk_get_rate((unsigned long)dt_uart_info.clock);
Yann Gautierd0714c02022-01-05 18:02:46 +0100267#endif
Yann Gautier7a819122021-10-18 15:26:33 +0200268
Yann Gautierd1435742021-10-18 10:55:23 +0200269 set_console(dt_uart_info.base, clk_rate);
Yann Gautier7a819122021-10-18 15:26:33 +0200270
271 return 0;
272}
273
Yann Gautierd1435742021-10-18 10:55:23 +0200274#if STM32MP_EARLY_CONSOLE
275void stm32mp_setup_early_console(void)
276{
277 plat_crash_console_init();
278 set_console(STM32MP_DEBUG_USART_BASE, STM32MP_DEBUG_USART_CLK_FRQ);
279}
280#endif /* STM32MP_EARLY_CONSOLE */
281
Yann Gautiered6515d2021-03-08 15:03:35 +0100282/*****************************************************************************
283 * plat_is_smccc_feature_available() - This function checks whether SMCCC
284 * feature is availabile for platform.
285 * @fid: SMCCC function id
286 *
287 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and
288 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise.
289 *****************************************************************************/
290int32_t plat_is_smccc_feature_available(u_register_t fid)
291{
292 switch (fid) {
293 case SMCCC_ARCH_SOC_ID:
294 return SMC_ARCH_CALL_SUCCESS;
295 default:
296 return SMC_ARCH_CALL_NOT_SUPPORTED;
297 }
298}
299
300/* Get SOC version */
301int32_t plat_get_soc_version(void)
302{
303 uint32_t chip_id = stm32mp_get_chip_dev_id();
304 uint32_t manfid = SOC_ID_SET_JEP_106(JEDEC_ST_BKID, JEDEC_ST_MFID);
305
306 return (int32_t)(manfid | (chip_id & SOC_ID_IMPL_DEF_MASK));
307}
308
309/* Get SOC revision */
310int32_t plat_get_soc_revision(void)
311{
312 return (int32_t)(stm32mp_get_chip_version() & SOC_ID_REV_MASK);
313}