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Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01001/*
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +00002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <stdbool.h>
8
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01009#include <arch.h>
10#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/el3_runtime/pubsub.h>
12#include <lib/extensions/spe.h>
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010013
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010014static inline void psb_csync(void)
15{
16 /*
17 * The assembler does not yet understand the psb csync mnemonic
18 * so use the equivalent hint instruction.
19 */
20 __asm__ volatile("hint #17");
21}
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010022
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010023bool spe_supported(void)
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010024{
25 uint64_t features;
26
27 features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT;
Andre Przywara7828f222020-09-11 09:18:09 +010028 return (features & ID_AA64DFR0_PMS_MASK) > 0ULL;
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000029}
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010030
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010031void spe_enable(bool el2_unused)
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000032{
33 uint64_t v;
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010034
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010035 if (!spe_supported())
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000036 return;
37
38 if (el2_unused) {
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010039 /*
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000040 * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical
41 * profiling controls to EL2.
42 *
43 * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure
44 * state. Accesses to profiling buffer controls at
45 * Non-secure EL1 are not trapped to EL2.
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010046 */
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000047 v = read_mdcr_el2();
48 v &= ~MDCR_EL2_TPMS;
49 v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1);
50 write_mdcr_el2(v);
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010051 }
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000052
53 /*
54 * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state
55 * and disabled in secure state. Accesses to SPE registers at
56 * S-EL1 generate trap exceptions to EL3.
57 */
58 v = read_mdcr_el3();
59 v |= MDCR_NSPB(MDCR_NSPB_EL1);
60 write_mdcr_el3(v);
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010061}
62
63void spe_disable(void)
64{
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000065 uint64_t v;
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010066
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010067 if (!spe_supported())
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000068 return;
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010069
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000070 /* Drain buffered data */
71 psb_csync();
72 dsbnsh();
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010073
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000074 /* Disable profiling buffer */
75 v = read_pmblimitr_el1();
76 v &= ~(1ULL << 0);
77 write_pmblimitr_el1(v);
78 isb();
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010079}
80
81static void *spe_drain_buffers_hook(const void *arg)
82{
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010083 if (!spe_supported())
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000084 return (void *)-1;
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010085
Dimitris Papastamos5e8cd792018-02-19 14:52:19 +000086 /* Drain buffered data */
87 psb_csync();
88 dsbnsh();
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +010089
90 return (void *)0;
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010091}
92
93SUBSCRIBE_TO_EVENT(cm_entering_secure_world, spe_drain_buffers_hook);