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Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001Arm Fixed Virtual Platforms (FVP)
2=================================
3
4Fixed Virtual Platform (FVP) Support
5------------------------------------
6
7This section lists the supported Arm |FVP| platforms. Please refer to the FVP
8documentation for a detailed description of the model parameter options.
9
10The latest version of the AArch64 build of TF-A has been tested on the following
11Arm FVPs without shifted affinities, and that do not support threaded CPU cores
12(64-bit host machine only).
13
14.. note::
laurenw-arm0a9b8d02020-04-15 17:48:36 -050015 The FVP models used are Version 11.9 Build 41, unless otherwise stated.
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010016
17- ``FVP_Base_AEMv8A-AEMv8A``
18- ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
19- ``FVP_Base_RevC-2xAEMv8A``
20- ``FVP_Base_Cortex-A32x4``
21- ``FVP_Base_Cortex-A35x4``
22- ``FVP_Base_Cortex-A53x4``
23- ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
24- ``FVP_Base_Cortex-A55x4``
25- ``FVP_Base_Cortex-A57x1-A53x1``
26- ``FVP_Base_Cortex-A57x2-A53x4``
27- ``FVP_Base_Cortex-A57x4-A53x4``
28- ``FVP_Base_Cortex-A57x4``
laurenw-arm0a9b8d02020-04-15 17:48:36 -050029- ``FVP_Base_Cortex-A65x4``
30- ``FVP_Base_Cortex-A65AEx8``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010031- ``FVP_Base_Cortex-A72x4-A53x4``
32- ``FVP_Base_Cortex-A72x4``
33- ``FVP_Base_Cortex-A73x4-A53x4``
34- ``FVP_Base_Cortex-A73x4``
35- ``FVP_Base_Cortex-A75x4``
36- ``FVP_Base_Cortex-A76x4``
37- ``FVP_Base_Cortex-A76AEx4``
38- ``FVP_Base_Cortex-A76AEx8``
laurenw-arm0a9b8d02020-04-15 17:48:36 -050039- ``FVP_Base_Cortex-A77x4``
Alexei Fedorovd6781fb2020-07-20 13:26:49 +010040- ``FVP_Base_Neoverse-E1x1``
41- ``FVP_Base_Neoverse-E1x2``
42- ``FVP_Base_Neoverse-E1x4``
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010043- ``FVP_Base_Neoverse-N1x4``
44- ``FVP_Base_Zeusx4``
Vijayenthiran Subramaniam9602ffe2020-07-22 22:08:28 +053045- ``FVP_CSS_SGI-575`` (Version 11.10 build 36)
laurenw-arm0a9b8d02020-04-15 17:48:36 -050046- ``FVP_CSS_SGM-775``
Vijayenthiran Subramaniam9602ffe2020-07-22 22:08:28 +053047- ``FVP_RD_E1_edge`` (Version 11.10 build 36)
48- ``FVP_RD_N1_edge`` (Version 11.10 build 36)
49- ``FVP_RD_N1_edge_dual`` (Version 11.10 build 36)
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +010050- ``Foundation_Platform``
51
52The latest version of the AArch32 build of TF-A has been tested on the
53following Arm FVPs without shifted affinities, and that do not support threaded
54CPU cores (64-bit host machine only).
55
56- ``FVP_Base_AEMv8A-AEMv8A``
57- ``FVP_Base_Cortex-A32x4``
58
59.. note::
60 The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
61 is not compatible with legacy GIC configurations. Therefore this FVP does not
62 support these legacy GIC configurations.
63
64The *Foundation* and *Base* FVPs can be downloaded free of charge. See the `Arm
65FVP website`_. The Cortex-A models listed above are also available to download
66from `Arm's website`_.
67
68.. note::
69 The build numbers quoted above are those reported by launching the FVP
70 with the ``--version`` parameter.
71
72.. note::
73 Linaro provides a ramdisk image in prebuilt FVP configurations and full
74 file systems that can be downloaded separately. To run an FVP with a virtio
75 file system image an additional FVP configuration option
76 ``-C bp.virtioblockdevice.image_path="<path-to>/<file-system-image>`` can be
77 used.
78
79.. note::
80 The software will not work on Version 1.0 of the Foundation FVP.
81 The commands below would report an ``unhandled argument`` error in this case.
82
83.. note::
84 FVPs can be launched with ``--cadi-server`` option such that a
85 CADI-compliant debugger (for example, Arm DS-5) can connect to and control
86 its execution.
87
88.. warning::
89 Since FVP model Version 11.0 Build 11.0.34 and Version 8.5 Build 0.8.5202
90 the internal synchronisation timings changed compared to older versions of
91 the models. The models can be launched with ``-Q 100`` option if they are
92 required to match the run time characteristics of the older versions.
93
94All the above platforms have been tested with `Linaro Release 19.06`_.
95
96.. _build_options_arm_fvp_platform:
97
98Arm FVP Platform Specific Build Options
99---------------------------------------
100
101- ``FVP_CLUSTER_COUNT`` : Configures the cluster count to be used to
102 build the topology tree within TF-A. By default TF-A is configured for dual
103 cluster topology and this option can be used to override the default value.
104
105- ``FVP_INTERCONNECT_DRIVER``: Selects the interconnect driver to be built. The
106 default interconnect driver depends on the value of ``FVP_CLUSTER_COUNT`` as
107 explained in the options below:
108
109 - ``FVP_CCI`` : The CCI driver is selected. This is the default
110 if 0 < ``FVP_CLUSTER_COUNT`` <= 2.
111 - ``FVP_CCN`` : The CCN driver is selected. This is the default
112 if ``FVP_CLUSTER_COUNT`` > 2.
113
114- ``FVP_MAX_CPUS_PER_CLUSTER``: Sets the maximum number of CPUs implemented in
115 a single cluster. This option defaults to 4.
116
117- ``FVP_MAX_PE_PER_CPU``: Sets the maximum number of PEs implemented on any CPU
118 in the system. This option defaults to 1. Note that the build option
119 ``ARM_PLAT_MT`` doesn't have any effect on FVP platforms.
120
121- ``FVP_USE_GIC_DRIVER`` : Selects the GIC driver to be built. Options:
122
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100123 - ``FVP_GICV2`` : The GICv2 only driver is selected
124 - ``FVP_GICV3`` : The GICv3 only driver is selected (default option)
125
126- ``FVP_USE_SP804_TIMER`` : Use the SP804 timer instead of the Generic Timer
127 for functions that wait for an arbitrary time length (udelay and mdelay).
128 The default value is 0.
129
130- ``FVP_HW_CONFIG_DTS`` : Specify the path to the DTS file to be compiled
131 to DTB and packaged in FIP as the HW_CONFIG. See :ref:`Firmware Design` for
132 details on HW_CONFIG. By default, this is initialized to a sensible DTS
133 file in ``fdts/`` folder depending on other build options. But some cases,
134 like shifted affinity format for MPIDR, cannot be detected at build time
135 and this option is needed to specify the appropriate DTS file.
136
137- ``FVP_HW_CONFIG`` : Specify the path to the HW_CONFIG blob to be packaged in
138 FIP. See :ref:`Firmware Design` for details on HW_CONFIG. This option is
139 similar to the ``FVP_HW_CONFIG_DTS`` option, but it directly specifies the
140 HW_CONFIG blob instead of the DTS file. This option is useful to override
141 the default HW_CONFIG selected by the build system.
142
143Booting Firmware Update images
144------------------------------
145
146When Firmware Update (FWU) is enabled there are at least 2 new images
147that have to be loaded, the Non-Secure FWU ROM (NS-BL1U), and the
148FWU FIP.
149
150The additional fip images must be loaded with:
151
152::
153
154 --data cluster0.cpu0="<path_to>/ns_bl1u.bin"@0x0beb8000 [ns_bl1u_base_address]
155 --data cluster0.cpu0="<path_to>/fwu_fip.bin"@0x08400000 [ns_bl2u_base_address]
156
157The address ns_bl1u_base_address is the value of NS_BL1U_BASE.
158In the same way, the address ns_bl2u_base_address is the value of
159NS_BL2U_BASE.
160
161Booting an EL3 payload
162----------------------
163
164The EL3 payloads boot flow requires the CPU's mailbox to be cleared at reset for
165the secondary CPUs holding pen to work properly. Unfortunately, its reset value
166is undefined on the FVP platform and the FVP platform code doesn't clear it.
167Therefore, one must modify the way the model is normally invoked in order to
168clear the mailbox at start-up.
169
170One way to do that is to create an 8-byte file containing all zero bytes using
171the following command:
172
173.. code:: shell
174
175 dd if=/dev/zero of=mailbox.dat bs=1 count=8
176
177and pre-load it into the FVP memory at the mailbox address (i.e. ``0x04000000``)
178using the following model parameters:
179
180::
181
182 --data cluster0.cpu0=mailbox.dat@0x04000000 [Base FVPs]
183 --data=mailbox.dat@0x04000000 [Foundation FVP]
184
185To provide the model with the EL3 payload image, the following methods may be
186used:
187
188#. If the EL3 payload is able to execute in place, it may be programmed into
189 flash memory. On Base Cortex and AEM FVPs, the following model parameter
190 loads it at the base address of the NOR FLASH1 (the NOR FLASH0 is already
191 used for the FIP):
192
193 ::
194
195 -C bp.flashloader1.fname="<path-to>/<el3-payload>"
196
197 On Foundation FVP, there is no flash loader component and the EL3 payload
198 may be programmed anywhere in flash using method 3 below.
199
200#. When using the ``SPIN_ON_BL1_EXIT=1`` loading method, the following DS-5
201 command may be used to load the EL3 payload ELF image over JTAG:
202
203 ::
204
205 load <path-to>/el3-payload.elf
206
207#. The EL3 payload may be pre-loaded in volatile memory using the following
208 model parameters:
209
210 ::
211
212 --data cluster0.cpu0="<path-to>/el3-payload>"@address [Base FVPs]
213 --data="<path-to>/<el3-payload>"@address [Foundation FVP]
214
215 The address provided to the FVP must match the ``EL3_PAYLOAD_BASE`` address
216 used when building TF-A.
217
218Booting a preloaded kernel image (Base FVP)
219-------------------------------------------
220
221The following example uses a simplified boot flow by directly jumping from the
222TF-A to the Linux kernel, which will use a ramdisk as filesystem. This can be
223useful if both the kernel and the device tree blob (DTB) are already present in
224memory (like in FVP).
225
226For example, if the kernel is loaded at ``0x80080000`` and the DTB is loaded at
227address ``0x82000000``, the firmware can be built like this:
228
229.. code:: shell
230
Madhukar Pappireddyc0ba2482020-01-10 16:11:18 -0600231 CROSS_COMPILE=aarch64-none-elf- \
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100232 make PLAT=fvp DEBUG=1 \
233 RESET_TO_BL31=1 \
234 ARM_LINUX_KERNEL_AS_BL33=1 \
235 PRELOADED_BL33_BASE=0x80080000 \
236 ARM_PRELOADED_DTB_BASE=0x82000000 \
237 all fip
238
239Now, it is needed to modify the DTB so that the kernel knows the address of the
240ramdisk. The following script generates a patched DTB from the provided one,
241assuming that the ramdisk is loaded at address ``0x84000000``. Note that this
242script assumes that the user is using a ramdisk image prepared for U-Boot, like
243the ones provided by Linaro. If using a ramdisk without this header,the ``0x40``
244offset in ``INITRD_START`` has to be removed.
245
246.. code:: bash
247
248 #!/bin/bash
249
250 # Path to the input DTB
251 KERNEL_DTB=<path-to>/<fdt>
252 # Path to the output DTB
253 PATCHED_KERNEL_DTB=<path-to>/<patched-fdt>
254 # Base address of the ramdisk
255 INITRD_BASE=0x84000000
256 # Path to the ramdisk
257 INITRD=<path-to>/<ramdisk.img>
258
259 # Skip uboot header (64 bytes)
260 INITRD_START=$(printf "0x%x" $((${INITRD_BASE} + 0x40)) )
261 INITRD_SIZE=$(stat -Lc %s ${INITRD})
262 INITRD_END=$(printf "0x%x" $((${INITRD_BASE} + ${INITRD_SIZE})) )
263
264 CHOSEN_NODE=$(echo \
265 "/ { \
266 chosen { \
267 linux,initrd-start = <${INITRD_START}>; \
268 linux,initrd-end = <${INITRD_END}>; \
269 }; \
270 };")
271
272 echo $(dtc -O dts -I dtb ${KERNEL_DTB}) ${CHOSEN_NODE} | \
273 dtc -O dtb -o ${PATCHED_KERNEL_DTB} -
274
275And the FVP binary can be run with the following command:
276
277.. code:: shell
278
279 <path-to>/FVP_Base_AEMv8A-AEMv8A \
280 -C pctl.startup=0.0.0.0 \
281 -C bp.secure_memory=1 \
282 -C cluster0.NUM_CORES=4 \
283 -C cluster1.NUM_CORES=4 \
284 -C cache_state_modelled=1 \
Alexei Fedorovea0424f2020-02-17 13:38:35 +0000285 -C cluster0.cpu0.RVBAR=0x04001000 \
286 -C cluster0.cpu1.RVBAR=0x04001000 \
287 -C cluster0.cpu2.RVBAR=0x04001000 \
288 -C cluster0.cpu3.RVBAR=0x04001000 \
289 -C cluster1.cpu0.RVBAR=0x04001000 \
290 -C cluster1.cpu1.RVBAR=0x04001000 \
291 -C cluster1.cpu2.RVBAR=0x04001000 \
292 -C cluster1.cpu3.RVBAR=0x04001000 \
293 --data cluster0.cpu0="<path-to>/bl31.bin"@0x04001000 \
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100294 --data cluster0.cpu0="<path-to>/<patched-fdt>"@0x82000000 \
295 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
296 --data cluster0.cpu0="<path-to>/<ramdisk.img>"@0x84000000
297
298Obtaining the Flattened Device Trees
299^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
300
301Depending on the FVP configuration and Linux configuration used, different
302FDT files are required. FDT source files for the Foundation and Base FVPs can
303be found in the TF-A source directory under ``fdts/``. The Foundation FVP has
304a subset of the Base FVP components. For example, the Foundation FVP lacks
305CLCD and MMC support, and has only one CPU cluster.
306
307.. note::
308 It is not recommended to use the FDTs built along the kernel because not
309 all FDTs are available from there.
310
311The dynamic configuration capability is enabled in the firmware for FVPs.
312This means that the firmware can authenticate and load the FDT if present in
313FIP. A default FDT is packaged into FIP during the build based on
314the build configuration. This can be overridden by using the ``FVP_HW_CONFIG``
315or ``FVP_HW_CONFIG_DTS`` build options (refer to
316:ref:`build_options_arm_fvp_platform` for details on the options).
317
318- ``fvp-base-gicv2-psci.dts``
319
320 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
321 affinities and with Base memory map configuration.
322
323- ``fvp-base-gicv2-psci-aarch32.dts``
324
325 For use with models such as the Cortex-A32 Base FVPs without shifted
326 affinities and running Linux in AArch32 state with Base memory map
327 configuration.
328
329- ``fvp-base-gicv3-psci.dts``
330
331 For use with models such as the Cortex-A57-A53 Base FVPs without shifted
332 affinities and with Base memory map configuration and Linux GICv3 support.
333
334- ``fvp-base-gicv3-psci-1t.dts``
335
336 For use with models such as the AEMv8-RevC Base FVP with shifted affinities,
337 single threaded CPUs, Base memory map configuration and Linux GICv3 support.
338
339- ``fvp-base-gicv3-psci-dynamiq.dts``
340
341 For use with models as the Cortex-A55-A75 Base FVPs with shifted affinities,
342 single cluster, single threaded CPUs, Base memory map configuration and Linux
343 GICv3 support.
344
345- ``fvp-base-gicv3-psci-aarch32.dts``
346
347 For use with models such as the Cortex-A32 Base FVPs without shifted
348 affinities and running Linux in AArch32 state with Base memory map
349 configuration and Linux GICv3 support.
350
351- ``fvp-foundation-gicv2-psci.dts``
352
353 For use with Foundation FVP with Base memory map configuration.
354
355- ``fvp-foundation-gicv3-psci.dts``
356
357 (Default) For use with Foundation FVP with Base memory map configuration
358 and Linux GICv3 support.
359
360
361Running on the Foundation FVP with reset to BL1 entrypoint
362^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
363
364The following ``Foundation_Platform`` parameters should be used to boot Linux with
3654 CPUs using the AArch64 build of TF-A.
366
367.. code:: shell
368
369 <path-to>/Foundation_Platform \
370 --cores=4 \
371 --arm-v8.0 \
372 --secure-memory \
373 --visualization \
374 --gicv3 \
375 --data="<path-to>/<bl1-binary>"@0x0 \
376 --data="<path-to>/<FIP-binary>"@0x08000000 \
377 --data="<path-to>/<kernel-binary>"@0x80080000 \
378 --data="<path-to>/<ramdisk-binary>"@0x84000000
379
380Notes:
381
382- BL1 is loaded at the start of the Trusted ROM.
383- The Firmware Image Package is loaded at the start of NOR FLASH0.
384- The firmware loads the FDT packaged in FIP to the DRAM. The FDT load address
385 is specified via the ``hw_config_addr`` property in `TB_FW_CONFIG for FVP`_.
386- The default use-case for the Foundation FVP is to use the ``--gicv3`` option
387 and enable the GICv3 device in the model. Note that without this option,
388 the Foundation FVP defaults to legacy (Versatile Express) memory map which
389 is not supported by TF-A.
390- In order for TF-A to run correctly on the Foundation FVP, the architecture
391 versions must match. The Foundation FVP defaults to the highest v8.x
392 version it supports but the default build for TF-A is for v8.0. To avoid
393 issues either start the Foundation FVP to use v8.0 architecture using the
394 ``--arm-v8.0`` option, or build TF-A with an appropriate value for
395 ``ARM_ARCH_MINOR``.
396
397Running on the AEMv8 Base FVP with reset to BL1 entrypoint
398^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
399
400The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
401with 8 CPUs using the AArch64 build of TF-A.
402
403.. code:: shell
404
405 <path-to>/FVP_Base_RevC-2xAEMv8A \
406 -C pctl.startup=0.0.0.0 \
407 -C bp.secure_memory=1 \
408 -C bp.tzc_400.diagnostics=1 \
409 -C cluster0.NUM_CORES=4 \
410 -C cluster1.NUM_CORES=4 \
411 -C cache_state_modelled=1 \
412 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
413 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
414 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
415 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
416
417.. note::
418 The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires
419 a specific DTS for all the CPUs to be loaded.
420
421Running on the AEMv8 Base FVP (AArch32) with reset to BL1 entrypoint
422^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
423
424The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
425with 8 CPUs using the AArch32 build of TF-A.
426
427.. code:: shell
428
429 <path-to>/FVP_Base_AEMv8A-AEMv8A \
430 -C pctl.startup=0.0.0.0 \
431 -C bp.secure_memory=1 \
432 -C bp.tzc_400.diagnostics=1 \
433 -C cluster0.NUM_CORES=4 \
434 -C cluster1.NUM_CORES=4 \
435 -C cache_state_modelled=1 \
436 -C cluster0.cpu0.CONFIG64=0 \
437 -C cluster0.cpu1.CONFIG64=0 \
438 -C cluster0.cpu2.CONFIG64=0 \
439 -C cluster0.cpu3.CONFIG64=0 \
440 -C cluster1.cpu0.CONFIG64=0 \
441 -C cluster1.cpu1.CONFIG64=0 \
442 -C cluster1.cpu2.CONFIG64=0 \
443 -C cluster1.cpu3.CONFIG64=0 \
444 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
445 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
446 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
447 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
448
449Running on the Cortex-A57-A53 Base FVP with reset to BL1 entrypoint
450^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
451
452The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
453boot Linux with 8 CPUs using the AArch64 build of TF-A.
454
455.. code:: shell
456
457 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
458 -C pctl.startup=0.0.0.0 \
459 -C bp.secure_memory=1 \
460 -C bp.tzc_400.diagnostics=1 \
461 -C cache_state_modelled=1 \
462 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
463 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
464 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
465 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
466
467Running on the Cortex-A32 Base FVP (AArch32) with reset to BL1 entrypoint
468^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
469
470The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
471boot Linux with 4 CPUs using the AArch32 build of TF-A.
472
473.. code:: shell
474
475 <path-to>/FVP_Base_Cortex-A32x4 \
476 -C pctl.startup=0.0.0.0 \
477 -C bp.secure_memory=1 \
478 -C bp.tzc_400.diagnostics=1 \
479 -C cache_state_modelled=1 \
480 -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \
481 -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \
482 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
483 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
484
485
486Running on the AEMv8 Base FVP with reset to BL31 entrypoint
487^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
488
489The following ``FVP_Base_RevC-2xAEMv8A`` parameters should be used to boot Linux
490with 8 CPUs using the AArch64 build of TF-A.
491
492.. code:: shell
493
494 <path-to>/FVP_Base_RevC-2xAEMv8A \
495 -C pctl.startup=0.0.0.0 \
496 -C bp.secure_memory=1 \
497 -C bp.tzc_400.diagnostics=1 \
498 -C cluster0.NUM_CORES=4 \
499 -C cluster1.NUM_CORES=4 \
500 -C cache_state_modelled=1 \
501 -C cluster0.cpu0.RVBAR=0x04010000 \
502 -C cluster0.cpu1.RVBAR=0x04010000 \
503 -C cluster0.cpu2.RVBAR=0x04010000 \
504 -C cluster0.cpu3.RVBAR=0x04010000 \
505 -C cluster1.cpu0.RVBAR=0x04010000 \
506 -C cluster1.cpu1.RVBAR=0x04010000 \
507 -C cluster1.cpu2.RVBAR=0x04010000 \
508 -C cluster1.cpu3.RVBAR=0x04010000 \
509 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
510 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
511 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
512 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
513 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
514 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
515
516Notes:
517
518- If Position Independent Executable (PIE) support is enabled for BL31
519 in this config, it can be loaded at any valid address for execution.
520
521- Since a FIP is not loaded when using BL31 as reset entrypoint, the
522 ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
523 parameter is needed to load the individual bootloader images in memory.
524 BL32 image is only needed if BL31 has been built to expect a Secure-EL1
525 Payload. For the same reason, the FDT needs to be compiled from the DT source
526 and loaded via the ``--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000``
527 parameter.
528
529- The ``FVP_Base_RevC-2xAEMv8A`` has shifted affinities and requires a
530 specific DTS for all the CPUs to be loaded.
531
532- The ``-C cluster<X>.cpu<Y>.RVBAR=@<base-address-of-bl31>`` parameter, where
533 X and Y are the cluster and CPU numbers respectively, is used to set the
534 reset vector for each core.
535
536- Changing the default value of ``ARM_TSP_RAM_LOCATION`` will also require
537 changing the value of
538 ``--data="<path-to><bl32-binary>"@<base-address-of-bl32>`` to the new value of
539 ``BL32_BASE``.
540
541
542Running on the AEMv8 Base FVP (AArch32) with reset to SP_MIN entrypoint
543^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
544
545The following ``FVP_Base_AEMv8A-AEMv8A`` parameters should be used to boot Linux
546with 8 CPUs using the AArch32 build of TF-A.
547
548.. code:: shell
549
550 <path-to>/FVP_Base_AEMv8A-AEMv8A \
551 -C pctl.startup=0.0.0.0 \
552 -C bp.secure_memory=1 \
553 -C bp.tzc_400.diagnostics=1 \
554 -C cluster0.NUM_CORES=4 \
555 -C cluster1.NUM_CORES=4 \
556 -C cache_state_modelled=1 \
557 -C cluster0.cpu0.CONFIG64=0 \
558 -C cluster0.cpu1.CONFIG64=0 \
559 -C cluster0.cpu2.CONFIG64=0 \
560 -C cluster0.cpu3.CONFIG64=0 \
561 -C cluster1.cpu0.CONFIG64=0 \
562 -C cluster1.cpu1.CONFIG64=0 \
563 -C cluster1.cpu2.CONFIG64=0 \
564 -C cluster1.cpu3.CONFIG64=0 \
565 -C cluster0.cpu0.RVBAR=0x04002000 \
566 -C cluster0.cpu1.RVBAR=0x04002000 \
567 -C cluster0.cpu2.RVBAR=0x04002000 \
568 -C cluster0.cpu3.RVBAR=0x04002000 \
569 -C cluster1.cpu0.RVBAR=0x04002000 \
570 -C cluster1.cpu1.RVBAR=0x04002000 \
571 -C cluster1.cpu2.RVBAR=0x04002000 \
572 -C cluster1.cpu3.RVBAR=0x04002000 \
573 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
574 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
575 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
576 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
577 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
578
579.. note::
580 The load address of ``<bl32-binary>`` depends on the value ``BL32_BASE``.
581 It should match the address programmed into the RVBAR register as well.
582
583Running on the Cortex-A57-A53 Base FVP with reset to BL31 entrypoint
584^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
585
586The following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to
587boot Linux with 8 CPUs using the AArch64 build of TF-A.
588
589.. code:: shell
590
591 <path-to>/FVP_Base_Cortex-A57x4-A53x4 \
592 -C pctl.startup=0.0.0.0 \
593 -C bp.secure_memory=1 \
594 -C bp.tzc_400.diagnostics=1 \
595 -C cache_state_modelled=1 \
596 -C cluster0.cpu0.RVBARADDR=0x04010000 \
597 -C cluster0.cpu1.RVBARADDR=0x04010000 \
598 -C cluster0.cpu2.RVBARADDR=0x04010000 \
599 -C cluster0.cpu3.RVBARADDR=0x04010000 \
600 -C cluster1.cpu0.RVBARADDR=0x04010000 \
601 -C cluster1.cpu1.RVBARADDR=0x04010000 \
602 -C cluster1.cpu2.RVBARADDR=0x04010000 \
603 -C cluster1.cpu3.RVBARADDR=0x04010000 \
604 --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \
605 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \
606 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
607 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
608 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
609 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
610
611Running on the Cortex-A32 Base FVP (AArch32) with reset to SP_MIN entrypoint
612^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
613
614The following ``FVP_Base_Cortex-A32x4`` model parameters should be used to
615boot Linux with 4 CPUs using the AArch32 build of TF-A.
616
617.. code:: shell
618
619 <path-to>/FVP_Base_Cortex-A32x4 \
620 -C pctl.startup=0.0.0.0 \
621 -C bp.secure_memory=1 \
622 -C bp.tzc_400.diagnostics=1 \
623 -C cache_state_modelled=1 \
624 -C cluster0.cpu0.RVBARADDR=0x04002000 \
625 -C cluster0.cpu1.RVBARADDR=0x04002000 \
626 -C cluster0.cpu2.RVBARADDR=0x04002000 \
627 -C cluster0.cpu3.RVBARADDR=0x04002000 \
628 --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000 \
629 --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
630 --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
631 --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \
632 --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000
633
634--------------
635
Imre Kisf05a1622020-02-27 15:05:03 +0100636*Copyright (c) 2019-2020, Arm Limited. All rights reserved.*
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100637
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500638.. _TB_FW_CONFIG for FVP: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100639.. _Arm's website: `FVP models`_
640.. _FVP models: https://developer.arm.com/products/system-design/fixed-virtual-platforms
641.. _Linaro Release 19.06: http://releases.linaro.org/members/arm/platforms/19.06
642.. _Arm FVP website: https://developer.arm.com/products/system-design/fixed-virtual-platforms