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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +05302 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved.
Nariman Poushin0ece80f2018-02-26 06:52:04 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
Chandni Cherukuri82718852018-08-02 12:29:07 +053010#include <cortex_a75.h>
John Tsichritzis56369c12019-02-19 13:49:06 +000011#include <neoverse_n1.h>
shriram.ke69c60b2021-08-11 17:39:30 +053012#include <neoverse_v1.h>
shriram.k0fef7b62021-08-11 17:36:17 +053013#include <neoverse_n2.h>
Deepak Pandeyb5615362018-10-11 13:44:43 +053014#include <cpu_macros.S>
Nariman Poushin0ece80f2018-02-26 06:52:04 +000015
Nariman Poushin0ece80f2018-02-26 06:52:04 +000016 .globl plat_arm_calc_core_pos
Chandni Cherukuri82718852018-08-02 12:29:07 +053017 .globl plat_reset_handler
Nariman Poushin0ece80f2018-02-26 06:52:04 +000018
19 /* -----------------------------------------------------
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053020 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
21 *
22 * Helper function to calculate the core position.
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +053023 * (ChipId * PLAT_ARM_CLUSTER_COUNT *
24 * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053025 * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
26 * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
27 * ThreadId
28 *
29 * which can be simplified as:
30 *
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +053031 * ((((ChipId * PLAT_ARM_CLUSTER_COUNT) + ClusterId) *
32 * CSS_SGI_MAX_CPUS_PER_CLUSTER) + CPUId) * CSS_SGI_MAX_PE_PER_CPU +
33 * ThreadId
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053034 * ------------------------------------------------------
35 */
36
Nariman Poushin0ece80f2018-02-26 06:52:04 +000037func plat_arm_calc_core_pos
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +053038 mov x4, x0
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053039
40 /*
41 * The MT bit in MPIDR is always set for SGI platforms
42 * and the affinity level 0 corresponds to thread affinity level.
43 */
44
45 /* Extract individual affinity fields from MPIDR */
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +053046 ubfx x0, x4, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
47 ubfx x1, x4, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
48 ubfx x2, x4, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
49 ubfx x3, x4, #MPIDR_AFF3_SHIFT, #MPIDR_AFFINITY_BITS
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053050
51 /* Compute linear position */
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +053052 mov x4, #PLAT_ARM_CLUSTER_COUNT
53 madd x2, x3, x4, x2
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053054 mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
55 madd x1, x2, x4, x1
Vijayenthiran Subramaniamdde6d3e2019-10-29 15:56:41 +053056 mov x4, #CSS_SGI_MAX_PE_PER_CPU
57 madd x0, x1, x4, x0
Nariman Poushin0ece80f2018-02-26 06:52:04 +000058 ret
59endfunc plat_arm_calc_core_pos
Chandni Cherukuri82718852018-08-02 12:29:07 +053060
Chandni Cherukuri82718852018-08-02 12:29:07 +053061 /* -----------------------------------------------------
62 * void plat_reset_handler(void);
63 *
64 * Determine the CPU MIDR and disable power down bit for
65 * that CPU.
66 * -----------------------------------------------------
67 */
68func plat_reset_handler
69 jump_if_cpu_midr CORTEX_A75_MIDR, A75
John Tsichritzis56369c12019-02-19 13:49:06 +000070 jump_if_cpu_midr NEOVERSE_N1_MIDR, N1
shriram.ke69c60b2021-08-11 17:39:30 +053071 jump_if_cpu_midr NEOVERSE_V1_MIDR, V1
shriram.k0fef7b62021-08-11 17:36:17 +053072 jump_if_cpu_midr NEOVERSE_N2_MIDR, N2
Chandni Cherukuri82718852018-08-02 12:29:07 +053073 ret
74
75 /* -----------------------------------------------------
76 * Disable CPU power down bit in power control register
77 * -----------------------------------------------------
78 */
79A75:
80 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
81 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
82 msr CORTEX_A75_CPUPWRCTLR_EL1, x0
83 isb
84 ret
Chandni Cherukuri044e27a2018-08-07 14:52:55 +053085
John Tsichritzis56369c12019-02-19 13:49:06 +000086N1:
87 mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
88 bic x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
89 msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
Chandni Cherukuri044e27a2018-08-07 14:52:55 +053090 isb
91 ret
shriram.ke69c60b2021-08-11 17:39:30 +053092
93V1:
94 mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
95 bic x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
96 msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
97 isb
98 ret
shriram.k0fef7b62021-08-11 17:36:17 +053099
100N2:
101 mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
102 bic x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
103 msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
104 isb
105 ret
Chandni Cherukuri82718852018-08-02 12:29:07 +0530106endfunc plat_reset_handler