| Karl Li | 130536e | 2023-04-21 11:43:24 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2023, MediaTek Inc. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef APUSYS_DEVAPC_DEF_H |
| 8 | #define APUSYS_DEVAPC_DEF_H |
| 9 | |
| 10 | #include <lib/mmio.h> |
| 11 | #include "../devapc/apusys_dapc_v1.h" |
| 12 | |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 13 | /* NoC */ |
| 14 | #define SLAVE_MD32_SRAM SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 15 | |
| Karl Li | 130536e | 2023-04-21 11:43:24 +0800 | [diff] [blame] | 16 | /* Control */ |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 17 | #define SLAVE_VCORE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 18 | #define SLAVE_RPC SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT |
| 19 | #define SLAVE_PCU SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 20 | #define SLAVE_AO_CTRL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 21 | #define SLAVE_PLL SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT |
| 22 | #define SLAVE_ACC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 23 | #define SLAVE_SEC SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 24 | #define SLAVE_ARE0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 25 | #define SLAVE_ARE1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 26 | #define SLAVE_ARE2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 27 | #define SLAVE_UNKNOWN SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 28 | #define SLAVE_APU_BULK SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 29 | #define SLAVE_AO_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 30 | #define SLAVE_AO_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 31 | #define SLAVE_AO_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| Chungying Lu | 50b17e7 | 2023-07-12 16:09:49 +0800 | [diff] [blame] | 32 | #define SLAVE_RCX_ACX_BULK SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 33 | #define SLAVE_ACX0_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 34 | #define SLAVE_RPCTOP_LITE_ACX0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Chungying Lu | 50b17e7 | 2023-07-12 16:09:49 +0800 | [diff] [blame] | 35 | #define SLAVE_ACX1_BCRM SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 36 | #define SLAVE_RPCTOP_LITE_ACX1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Chungying Lu | 50b17e7 | 2023-07-12 16:09:49 +0800 | [diff] [blame] | 37 | #define SLAVE_RCX_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 38 | #define SLAVE_RCX_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Chungying Lu | 50b17e7 | 2023-07-12 16:09:49 +0800 | [diff] [blame] | 39 | #define SLAVE_SAE_TO_ACX0_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 40 | #define SLAVE_SAE_TO_ACX0_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 41 | #define SLAVE_RCX_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 42 | #define SLAVE_RCX_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 43 | #define SLAVE_SAE_TO_ACX1_0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 44 | #define SLAVE_SAE_TO_ACX1_1 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 45 | #define SLAVE_MD32_SYSCTRL0 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 46 | #define SLAVE_MD32_SYSCTRL1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT |
| 47 | #define SLAVE_MD32_WDT SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 48 | #define SLAVE_MD32_CACHE SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 49 | #define SLAVE_NOC_AXI SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 50 | #define SLAVE_MD32_DBG SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 51 | #define SLAVE_DBG_CRTL SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 52 | #define SLAVE_IOMMU0_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 53 | #define SLAVE_IOMMU0_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 54 | #define SLAVE_IOMMU0_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 55 | #define SLAVE_IOMMU0_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 56 | #define SLAVE_IOMMU0_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 57 | #define SLAVE_IOMMU1_BANK0 SLAVE_FORBID_EXCEPT_D0_D5_NO_PROTECT |
| 58 | #define SLAVE_IOMMU1_BANK1 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 59 | #define SLAVE_IOMMU1_BANK2 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 60 | #define SLAVE_IOMMU1_BANK3 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 61 | #define SLAVE_IOMMU1_BANK4 SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 62 | #define SLAVE_S0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 63 | #define SLAVE_N0_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 64 | #define SLAVE_ACP_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 65 | #define SLAVE_S1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 66 | #define SLAVE_N1_SSC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 67 | #define SLAVE_CFG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT |
| 68 | #define SLAVE_SEMA_STIMER SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 69 | #define SLAVE_EMI_CFG SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 70 | #define SLAVE_LOG SLAVE_FORBID_EXCEPT_D0_SEC_RW_NS_R_D5_NO_PROTECT |
| 71 | #define SLAVE_CPE_SENSOR SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 72 | #define SLAVE_CPE_COEF SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 73 | #define SLAVE_CPE_CTRL SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 74 | #define SLAVE_DFD_REG_SOC SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 75 | #define SLAVE_SENSOR_WRAP_ACX0_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 76 | #define SLAVE_SENSOR_WRAP_ACX0_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 77 | #define SLAVE_SENSOR_WRAP_ACX0_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 78 | #define SLAVE_SENSOR_WRAP_ACX1_DLA0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 79 | #define SLAVE_SENSOR_WRAP_ACX1_DLA1 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 80 | #define SLAVE_SENSOR_WRAP_ACX1_VPU0 SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 81 | #define SLAVE_REVISER SLAVE_FORBID_EXCEPT_D0_SEC_RW |
| Chungying Lu | 50b17e7 | 2023-07-12 16:09:49 +0800 | [diff] [blame] | 82 | #define SLAVE_NOC SLAVE_FORBID_EXCEPT_D0_SEC_RW |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 83 | #define SLAVE_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 84 | #define SLAVE_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 85 | #define SLAVE_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 86 | #define SLAVE_NOC_DAPC_WRAP SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 87 | #define SLAVE_NOC_DAPC_CON SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 88 | #define SLAVE_NOC_BCRM SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 89 | #define SLAVE_ACS SLAVE_FORBID_EXCEPT_D0_SEC_RW_D5_NO_PROTECT |
| 90 | #define SLAVE_HSE SLAVE_FORBID_EXCEPT_D5_NO_PROTECT |
| 91 | |
| Karl Li | 130536e | 2023-04-21 11:43:24 +0800 | [diff] [blame] | 92 | |
| 93 | /* Power Domain: AO */ |
| 94 | #define APU_CTRL_DAPC_AO_SLAVE_NUM_IN_1_DOM (16) |
| 95 | #define APU_CTRL_DAPC_AO_DOM_NUM (16) |
| 96 | #define APU_CTRL_DAPC_AO_SLAVE_NUM (30) |
| 97 | #define DEVAPC_MASK (0x3U) |
| 98 | #define DEVAPC_DOM_SHIFT (2) |
| 99 | |
| Karl Li | 03facb0 | 2023-04-24 16:45:49 +0800 | [diff] [blame] | 100 | /* Power Domain: RCX */ |
| 101 | #define APU_CTRL_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16) |
| 102 | #define APU_CTRL_DAPC_RCX_DOM_NUM (16) |
| 103 | #define APU_CTRL_DAPC_RCX_SLAVE_NUM (63) |
| 104 | |
| 105 | #define APU_NOC_DAPC_RCX_SLAVE_NUM_IN_1_DOM (16) |
| 106 | #define APU_NOC_DAPC_RCX_DOM_NUM (16) |
| 107 | #define APU_NOC_DAPC_RCX_SLAVE_NUM (5) |
| 108 | |
| Karl Li | 130536e | 2023-04-21 11:43:24 +0800 | [diff] [blame] | 109 | #endif /* APUSYS_DEVAPC_DEF_H */ |