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Haojian Zhuang602362d2017-06-01 12:15:14 +08001/*
Arthur Cassegrain98fe4c42021-11-26 16:34:36 +01002 * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang602362d2017-06-01 12:15:14 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef HIKEY960_DEF_H
8#define HIKEY960_DEF_H
Haojian Zhuang602362d2017-06-01 12:15:14 +08009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
11#include <plat/common/common_def.h>
Haojian Zhuang602362d2017-06-01 12:15:14 +080012
13#define DDR_BASE 0x0
Joel Hutton424925a2018-12-27 13:42:19 +000014#define DDR_SIZE 0xE0000000
Haojian Zhuang602362d2017-06-01 12:15:14 +080015
16#define DEVICE_BASE 0xE0000000
17#define DEVICE_SIZE 0x20000000
18
Victor Chong91287682017-05-28 00:14:37 +090019/* Memory location options for TSP */
20#define HIKEY960_SRAM_ID 0
21#define HIKEY960_DRAM_ID 1
22
23/*
Lukas Hanel8a4de612022-03-01 14:18:22 +010024 * DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several
Victor Chong91287682017-05-28 00:14:37 +090025 * regions:
Lukas Hanel8a4de612022-03-01 14:18:22 +010026 * - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE
Lukas Hanel5258be12022-03-01 17:02:31 +010027 * - Datastore for SPMC_AT_EL3 (4MB at the top) used by BL31
28 * - Secure DDR (default is the top 60MB) used by OP-TEE
Victor Chong91287682017-05-28 00:14:37 +090029 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
30 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
31 * - Non-secure DDR (8MB) reserved for OP-TEE's future use
32 */
Lukas Hanel5258be12022-03-01 17:02:31 +010033#define DDR_SEC_SIZE 0x03C00000 /* reserve 60MB secure memory */
Victor Chong91287682017-05-28 00:14:37 +090034#define DDR_SEC_BASE 0x3F000000
Lukas Hanel5258be12022-03-01 17:02:31 +010035#define DDR2_SEC_SIZE 0x00400000 /* SPMC_AT_EL3: 4MB for BL31 RAM2 */
36#define DDR2_SEC_BASE 0x42C00000
Lukas Hanel8a4de612022-03-01 14:18:22 +010037#define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */
38#define DDR_SEC_CONFIG_BASE 0x43000000
Victor Chong91287682017-05-28 00:14:37 +090039
40#define DDR_SDP_SIZE 0x00400000
41#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
42 DDR_SDP_SIZE)
43
Haojian Zhuang602362d2017-06-01 12:15:14 +080044/*
45 * PL011 related constants
46 */
47#define PL011_UART5_BASE 0xFDF05000
48#define PL011_UART6_BASE 0xFFF32000
49#define PL011_BAUDRATE 115200
50#define PL011_UART_CLK_IN_HZ 19200000
51
52#define UFS_BASE 0
Haojian Zhuang602362d2017-06-01 12:15:14 +080053
54#define HIKEY960_UFS_DESC_BASE 0x20000000
55#define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */
56#define HIKEY960_UFS_DATA_BASE 0x10000000
57#define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */
58
Lukas Hanelcb91cb12022-03-01 15:40:39 +010059#if defined(SPMC_AT_EL3)
60/*
61 * Number of Secure Partitions supported.
62 * SPMC at EL3, uses this count to configure the maximum number of supported
63 * secure partitions.
64 */
65#define SECURE_PARTITION_COUNT 1
66
67/*
68 * Number of Nwld Partitions supported.
69 * SPMC at EL3, uses this count to configure the maximum number of supported
70 * nwld partitions.
71 */
72#define NS_PARTITION_COUNT 1
73/*
74 * Number of Logical Partitions supported.
75 * SPMC at EL3, uses this count to configure the maximum number of supported
76 * logical partitions.
77 */
78#define MAX_EL3_LP_DESCS_COUNT 1
79
80#endif /* SPMC_AT_EL3 */
81
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +000082#endif /* HIKEY960_DEF_H */