feat(hikey960): define a datastore for SPMC_AT_EL3
Kinibi now has 60MB (instead of 64MB).
Increase XLAT tables for BL31
Change-Id: I6843d26198a7d8bdb812e394e4482b1c35afa4c0
Signed-off-by: vallau01 <valentin.laurent@trustonic.com>
Signed-off-by: Lukas Hanel <lukas.hanel@trustonic.com>
diff --git a/plat/hisilicon/hikey960/hikey960_def.h b/plat/hisilicon/hikey960/hikey960_def.h
index 69a67d5..38d96c2 100644
--- a/plat/hisilicon/hikey960/hikey960_def.h
+++ b/plat/hisilicon/hikey960/hikey960_def.h
@@ -24,13 +24,16 @@
* DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several
* regions:
* - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE
- * - Secure DDR (default is the top 64MB) used by OP-TEE
+ * - Datastore for SPMC_AT_EL3 (4MB at the top) used by BL31
+ * - Secure DDR (default is the top 60MB) used by OP-TEE
* - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
* - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
* - Non-secure DDR (8MB) reserved for OP-TEE's future use
*/
-#define DDR_SEC_SIZE 0x04000000 /* reserve 64MB secure memory */
+#define DDR_SEC_SIZE 0x03C00000 /* reserve 60MB secure memory */
#define DDR_SEC_BASE 0x3F000000
+#define DDR2_SEC_SIZE 0x00400000 /* SPMC_AT_EL3: 4MB for BL31 RAM2 */
+#define DDR2_SEC_BASE 0x42C00000
#define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */
#define DDR_SEC_CONFIG_BASE 0x43000000