Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 1 | /* |
Arthur Cassegrain | 98fe4c4 | 2021-11-26 16:34:36 +0100 | [diff] [blame] | 2 | * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved. |
Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 7 | #ifndef HIKEY960_DEF_H |
| 8 | #define HIKEY960_DEF_H |
Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 9 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/tbbr/tbbr_img_def.h> |
| 11 | #include <plat/common/common_def.h> |
Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 12 | |
| 13 | #define DDR_BASE 0x0 |
Joel Hutton | 424925a | 2018-12-27 13:42:19 +0000 | [diff] [blame] | 14 | #define DDR_SIZE 0xE0000000 |
Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 15 | |
| 16 | #define DEVICE_BASE 0xE0000000 |
| 17 | #define DEVICE_SIZE 0x20000000 |
| 18 | |
Victor Chong | 9128768 | 2017-05-28 00:14:37 +0900 | [diff] [blame] | 19 | /* Memory location options for TSP */ |
| 20 | #define HIKEY960_SRAM_ID 0 |
| 21 | #define HIKEY960_DRAM_ID 1 |
| 22 | |
| 23 | /* |
Lukas Hanel | 8a4de61 | 2022-03-01 14:18:22 +0100 | [diff] [blame^] | 24 | * DDR for TEE (80MB from 0x3E00000-0x43000FFF) is divided into several |
Victor Chong | 9128768 | 2017-05-28 00:14:37 +0900 | [diff] [blame] | 25 | * regions: |
Lukas Hanel | 8a4de61 | 2022-03-01 14:18:22 +0100 | [diff] [blame^] | 26 | * - SPMC manifest (4KB at the top) used by SPMC_AT_EL3 and the TEE |
Arthur Cassegrain | 98fe4c4 | 2021-11-26 16:34:36 +0100 | [diff] [blame] | 27 | * - Secure DDR (default is the top 64MB) used by OP-TEE |
Victor Chong | 9128768 | 2017-05-28 00:14:37 +0900 | [diff] [blame] | 28 | * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) |
| 29 | * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature |
| 30 | * - Non-secure DDR (8MB) reserved for OP-TEE's future use |
| 31 | */ |
Arthur Cassegrain | 98fe4c4 | 2021-11-26 16:34:36 +0100 | [diff] [blame] | 32 | #define DDR_SEC_SIZE 0x04000000 /* reserve 64MB secure memory */ |
Victor Chong | 9128768 | 2017-05-28 00:14:37 +0900 | [diff] [blame] | 33 | #define DDR_SEC_BASE 0x3F000000 |
Lukas Hanel | 8a4de61 | 2022-03-01 14:18:22 +0100 | [diff] [blame^] | 34 | #define DDR_SEC_CONFIG_SIZE 0x00001000 /* SPMC_AT_EL3: SPMC manifest */ |
| 35 | #define DDR_SEC_CONFIG_BASE 0x43000000 |
Victor Chong | 9128768 | 2017-05-28 00:14:37 +0900 | [diff] [blame] | 36 | |
| 37 | #define DDR_SDP_SIZE 0x00400000 |
| 38 | #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ |
| 39 | DDR_SDP_SIZE) |
| 40 | |
Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 41 | /* |
| 42 | * PL011 related constants |
| 43 | */ |
| 44 | #define PL011_UART5_BASE 0xFDF05000 |
| 45 | #define PL011_UART6_BASE 0xFFF32000 |
| 46 | #define PL011_BAUDRATE 115200 |
| 47 | #define PL011_UART_CLK_IN_HZ 19200000 |
| 48 | |
| 49 | #define UFS_BASE 0 |
Haojian Zhuang | 602362d | 2017-06-01 12:15:14 +0800 | [diff] [blame] | 50 | |
| 51 | #define HIKEY960_UFS_DESC_BASE 0x20000000 |
| 52 | #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ |
| 53 | #define HIKEY960_UFS_DATA_BASE 0x10000000 |
| 54 | #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ |
| 55 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame] | 56 | #endif /* HIKEY960_DEF_H */ |