Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Robert Wakim | 48e6b57 | 2021-10-21 15:39:56 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 7 | #include <arch.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 8 | #include <asm_macros.S> |
| 9 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 10 | .globl flush_dcache_range |
Robert Wakim | 48e6b57 | 2021-10-21 15:39:56 +0100 | [diff] [blame] | 11 | .globl flush_dcache_to_popa_range |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 12 | .globl flush_dcache_to_popa_range_mte2 |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 13 | .globl clean_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | .globl inv_dcache_range |
| 15 | .globl dcsw_op_louis |
| 16 | .globl dcsw_op_all |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 17 | .globl dcsw_op_level1 |
| 18 | .globl dcsw_op_level2 |
| 19 | .globl dcsw_op_level3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 20 | |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 21 | /* Opcodes for data cache maintenance by PA instructions. */ |
| 22 | |
| 23 | /* |
| 24 | * sys #6, c7, c14, #1, x0 |
| 25 | * DC CIPAPA, X0 |
| 26 | */ |
| 27 | #define dc_cipapa_x0 0xd50e7e20 |
| 28 | |
| 29 | /* |
| 30 | * sys #6, c7, c14, #3, x0 |
| 31 | * DC CIDGPAPA, X0 |
| 32 | */ |
| 33 | #define dc_cigdpapa_x0 0xd50e7ea0 |
| 34 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 35 | /* |
| 36 | * This macro can be used for implementing various data cache operations `op` |
| 37 | */ |
| 38 | .macro do_dcache_maintenance_by_mva op |
Soby Mathew | f7e8aee | 2017-06-15 16:18:45 +0100 | [diff] [blame] | 39 | /* Exit early if size is zero */ |
| 40 | cbz x1, exit_loop_\op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 41 | dcache_line_size x2, x3 |
| 42 | add x1, x0, x1 |
| 43 | sub x3, x2, #1 |
| 44 | bic x0, x0, x3 |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 45 | loop_\op: |
| 46 | dc \op, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | add x0, x0, x2 |
| 48 | cmp x0, x1 |
Petre-Ionut Tudor | e5a6fef | 2019-11-07 15:18:03 +0000 | [diff] [blame] | 49 | b.lo loop_\op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | dsb sy |
Soby Mathew | f7e8aee | 2017-06-15 16:18:45 +0100 | [diff] [blame] | 51 | exit_loop_\op: |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 52 | ret |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 53 | .endm |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 54 | |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 55 | /* op: the hexadecimal instruction opcode for the cache operation */ |
| 56 | .macro do_dcache_maintenance_instr op |
| 57 | /* Exit early if size is zero */ |
| 58 | cbz x1, exit_loop_\op |
| 59 | dcache_line_size x2, x3 |
| 60 | sub x3, x2, #1 |
| 61 | bic x0, x0, x3 |
| 62 | add x1, x1, x0 |
| 63 | loop_\op: |
| 64 | .inst \op |
| 65 | add x0, x0, x2 |
| 66 | cmp x0, x1 |
| 67 | b.lo loop_\op |
| 68 | dsb osh |
| 69 | exit_loop_\op: |
| 70 | ret |
| 71 | .endm |
| 72 | |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 73 | .macro check_plat_can_cmo |
| 74 | #if CONDITIONAL_CMO |
| 75 | mov x3, x30 |
| 76 | mov x2, x0 |
| 77 | bl plat_can_cmo |
| 78 | mov x30, x3 |
| 79 | cbnz x0, 1f |
| 80 | ret |
| 81 | 1: |
| 82 | mov x0, x2 |
| 83 | #endif |
| 84 | .endm |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 85 | |
| 86 | /* ------------------------------------------- |
| 87 | * DCache Clean+Invalidate by MVA from base |
| 88 | * address till size. 'x0' = addr, 'x1' = size |
| 89 | * ------------------------------------------- |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 90 | */ |
| 91 | func flush_dcache_range |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 92 | check_plat_can_cmo |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 93 | do_dcache_maintenance_by_mva civac |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 94 | endfunc flush_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 95 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 96 | /* ------------------------------------------ |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 97 | * DCache Clean by MVA from base address till |
| 98 | * size. 'x0' = addr, 'x1' = size |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 99 | * ------------------------------------------ |
| 100 | */ |
| 101 | func clean_dcache_range |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 102 | check_plat_can_cmo |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 103 | do_dcache_maintenance_by_mva cvac |
| 104 | endfunc clean_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 105 | |
| 106 | /* ------------------------------------------ |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 107 | * DCache Invalidate by MVA from base address |
| 108 | * till size. 'x0' = addr, 'x1' = size |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 109 | * ------------------------------------------ |
| 110 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 111 | func inv_dcache_range |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 112 | check_plat_can_cmo |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 113 | do_dcache_maintenance_by_mva ivac |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 114 | endfunc inv_dcache_range |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | |
Robert Wakim | 48e6b57 | 2021-10-21 15:39:56 +0100 | [diff] [blame] | 116 | /* |
Robert Wakim | 48e6b57 | 2021-10-21 15:39:56 +0100 | [diff] [blame] | 117 | * ------------------------------------------ |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 118 | * DCache Clean+Invalidate by PA to POPA from |
| 119 | * base address till size. |
Robert Wakim | 48e6b57 | 2021-10-21 15:39:56 +0100 | [diff] [blame] | 120 | * 'x0' = addr, 'x1' = size |
| 121 | * ------------------------------------------ |
| 122 | */ |
| 123 | func flush_dcache_to_popa_range |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 124 | check_plat_can_cmo |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 125 | /* dc cipapa, x0 */ |
| 126 | do_dcache_maintenance_instr dc_cipapa_x0 |
Robert Wakim | 48e6b57 | 2021-10-21 15:39:56 +0100 | [diff] [blame] | 127 | endfunc flush_dcache_to_popa_range |
| 128 | |
Olivier Deprez | c80d0de | 2024-01-17 15:12:04 +0100 | [diff] [blame] | 129 | /* |
| 130 | * ------------------------------------------ |
| 131 | * Clean+Invalidate by PA to POPA (MTE2) |
| 132 | * from base address till size. |
| 133 | * 'x0' = addr, 'x1' = size |
| 134 | * ------------------------------------------ |
| 135 | * On implementations with FEAT_MTE2, Root firmware must issue |
| 136 | * DC_CIGDPAPA instead of DC_CIPAPA, in order to additionally |
| 137 | * clean and invalidate Allocation Tags associated with the |
| 138 | * affected locations. |
| 139 | */ |
| 140 | func flush_dcache_to_popa_range_mte2 |
| 141 | check_plat_can_cmo |
| 142 | /* dc cigdpapa, x0 */ |
| 143 | do_dcache_maintenance_instr dc_cigdpapa_x0 |
| 144 | endfunc flush_dcache_to_popa_range_mte2 |
| 145 | |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 146 | /* --------------------------------------------------------------- |
| 147 | * Data cache operations by set/way to the level specified |
| 148 | * |
| 149 | * The main function, do_dcsw_op requires: |
| 150 | * x0: The operation type (0-2), as defined in arch.h |
| 151 | * x3: The last cache level to operate on |
| 152 | * x9: clidr_el1 |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 153 | * x10: The cache level to begin operation from |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 154 | * and will carry out the operation on each data cache from level 0 |
| 155 | * to the level in x3 in sequence |
| 156 | * |
| 157 | * The dcsw_op macro sets up the x3 and x9 parameters based on |
| 158 | * clidr_el1 cache information before invoking the main function |
| 159 | * --------------------------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 160 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 161 | |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 162 | .macro dcsw_op shift, fw, ls |
| 163 | mrs x9, clidr_el1 |
| 164 | ubfx x3, x9, \shift, \fw |
| 165 | lsl x3, x3, \ls |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 166 | mov x10, xzr |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 167 | b do_dcsw_op |
| 168 | .endm |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 169 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 170 | func do_dcsw_op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 171 | cbz x3, exit |
johpow01 | 74b7e44 | 2021-12-01 13:18:30 -0600 | [diff] [blame] | 172 | mrs x12, ID_AA64MMFR2_EL1 // stash FEAT_CCIDX identifier in x12 |
| 173 | ubfx x12, x12, #ID_AA64MMFR2_EL1_CCIDX_SHIFT, #ID_AA64MMFR2_EL1_CCIDX_LENGTH |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 174 | adr x14, dcsw_loop_table // compute inner loop address |
| 175 | add x14, x14, x0, lsl #5 // inner loop is 8x32-bit instructions |
Alexei Fedorov | 90f2e88 | 2019-05-24 12:17:09 +0100 | [diff] [blame] | 176 | #if ENABLE_BTI |
| 177 | add x14, x14, x0, lsl #2 // inner loop is + "bti j" instruction |
| 178 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 179 | mov x0, x9 |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 180 | mov w8, #1 |
| 181 | loop1: |
| 182 | add x2, x10, x10, lsr #1 // work out 3x current cache level |
| 183 | lsr x1, x0, x2 // extract cache type bits from clidr |
| 184 | and x1, x1, #7 // mask the bits for current cache only |
| 185 | cmp x1, #2 // see what cache we have at this level |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 186 | b.lo level_done // nothing to do if no cache or icache |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 187 | |
| 188 | msr csselr_el1, x10 // select current cache level in csselr |
| 189 | isb // isb to sych the new cssr&csidr |
| 190 | mrs x1, ccsidr_el1 // read the new ccsidr |
| 191 | and x2, x1, #7 // extract the length of the cache lines |
| 192 | add x2, x2, #4 // add 4 (line length offset) |
johpow01 | 74b7e44 | 2021-12-01 13:18:30 -0600 | [diff] [blame] | 193 | |
| 194 | cbz x12, 1f // check for FEAT_CCIDX for Associativity |
| 195 | ubfx x4, x1, #3, #21 // x4 = associativity CCSIDR_EL1[23:3] |
| 196 | b 2f |
| 197 | 1: |
| 198 | ubfx x4, x1, #3, #10 // x4 = associativity CCSIDR_EL1[12:3] |
| 199 | 2: |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 200 | clz w5, w4 // bit position of way size increment |
| 201 | lsl w9, w4, w5 // w9 = aligned max way number |
| 202 | lsl w16, w8, w5 // w16 = way number loop decrement |
| 203 | orr w9, w10, w9 // w9 = combine way and cache number |
johpow01 | 74b7e44 | 2021-12-01 13:18:30 -0600 | [diff] [blame] | 204 | |
| 205 | cbz x12, 3f // check for FEAT_CCIDX for NumSets |
| 206 | ubfx x6, x1, #32, #24 // x6 (w6) = numsets CCSIDR_EL1[55:32] |
| 207 | // ISA will not allow x->w ubfx |
| 208 | b 4f |
| 209 | 3: |
| 210 | ubfx w6, w1, #13, #15 // w6 = numsets CCSIDR_EL1[27:13] |
| 211 | 4: |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 212 | lsl w17, w8, w2 // w17 = set number loop decrement |
| 213 | dsb sy // barrier before we start this level |
| 214 | br x14 // jump to DC operation specific loop |
| 215 | |
| 216 | .macro dcsw_loop _op |
Alexei Fedorov | 90f2e88 | 2019-05-24 12:17:09 +0100 | [diff] [blame] | 217 | #if ENABLE_BTI |
| 218 | bti j |
| 219 | #endif |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 220 | loop2_\_op: |
| 221 | lsl w7, w6, w2 // w7 = aligned max set number |
| 222 | |
| 223 | loop3_\_op: |
| 224 | orr w11, w9, w7 // combine cache, way and set number |
| 225 | dc \_op, x11 |
| 226 | subs w7, w7, w17 // decrement set number |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 227 | b.hs loop3_\_op |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 228 | |
| 229 | subs x9, x9, x16 // decrement way number |
Douglas Raillard | 9d92e8c | 2017-03-07 16:36:14 +0000 | [diff] [blame] | 230 | b.hs loop2_\_op |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 231 | |
| 232 | b level_done |
| 233 | .endm |
| 234 | |
| 235 | level_done: |
| 236 | add x10, x10, #2 // increment cache number |
| 237 | cmp x3, x10 |
Petre-Ionut Tudor | e5a6fef | 2019-11-07 15:18:03 +0000 | [diff] [blame] | 238 | b.hi loop1 |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 239 | msr csselr_el1, xzr // select cache level 0 in csselr |
| 240 | dsb sy // barrier to complete final cache operation |
| 241 | isb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 242 | exit: |
| 243 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 244 | endfunc do_dcsw_op |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 245 | |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 246 | dcsw_loop_table: |
| 247 | dcsw_loop isw |
| 248 | dcsw_loop cisw |
| 249 | dcsw_loop csw |
| 250 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 251 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 252 | func dcsw_op_louis |
Okash Khawaja | 9453220 | 2022-11-14 12:50:30 +0000 | [diff] [blame] | 253 | check_plat_can_cmo |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 254 | dcsw_op #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 255 | endfunc dcsw_op_louis |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 256 | |
| 257 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 258 | func dcsw_op_all |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 259 | check_plat_can_cmo |
Andrew Thoelke | 6a5b3a4 | 2014-04-25 10:49:30 +0100 | [diff] [blame] | 260 | dcsw_op #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 261 | endfunc dcsw_op_all |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 262 | |
| 263 | /* --------------------------------------------------------------- |
| 264 | * Helper macro for data cache operations by set/way for the |
| 265 | * level specified |
| 266 | * --------------------------------------------------------------- |
| 267 | */ |
| 268 | .macro dcsw_op_level level |
| 269 | mrs x9, clidr_el1 |
| 270 | mov x3, \level |
| 271 | sub x10, x3, #2 |
| 272 | b do_dcsw_op |
| 273 | .endm |
| 274 | |
| 275 | /* --------------------------------------------------------------- |
| 276 | * Data cache operations by set/way for level 1 cache |
| 277 | * |
| 278 | * The main function, do_dcsw_op requires: |
| 279 | * x0: The operation type (0-2), as defined in arch.h |
| 280 | * --------------------------------------------------------------- |
| 281 | */ |
| 282 | func dcsw_op_level1 |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 283 | check_plat_can_cmo |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 284 | dcsw_op_level #(1 << LEVEL_SHIFT) |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 285 | endfunc dcsw_op_level1 |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 286 | |
| 287 | /* --------------------------------------------------------------- |
| 288 | * Data cache operations by set/way for level 2 cache |
| 289 | * |
| 290 | * The main function, do_dcsw_op requires: |
| 291 | * x0: The operation type (0-2), as defined in arch.h |
| 292 | * --------------------------------------------------------------- |
| 293 | */ |
| 294 | func dcsw_op_level2 |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 295 | check_plat_can_cmo |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 296 | dcsw_op_level #(2 << LEVEL_SHIFT) |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 297 | endfunc dcsw_op_level2 |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 298 | |
| 299 | /* --------------------------------------------------------------- |
| 300 | * Data cache operations by set/way for level 3 cache |
| 301 | * |
| 302 | * The main function, do_dcsw_op requires: |
| 303 | * x0: The operation type (0-2), as defined in arch.h |
| 304 | * --------------------------------------------------------------- |
| 305 | */ |
| 306 | func dcsw_op_level3 |
Okash Khawaja | 037b56e | 2022-11-04 12:38:01 +0000 | [diff] [blame] | 307 | check_plat_can_cmo |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 308 | dcsw_op_level #(3 << LEVEL_SHIFT) |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 309 | endfunc dcsw_op_level3 |