| Zelalem Aweke | 688fbf7 | 2021-07-09 11:37:10 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | |
| 11 | .globl bl2_run_next_image |
| 12 | |
| 13 | |
| 14 | func bl2_run_next_image |
| 15 | mov r8,r0 |
| 16 | |
| 17 | /* |
| 18 | * MMU needs to be disabled because both BL2 and BL32 execute |
| 19 | * in PL1, and therefore share the same address space. |
| 20 | * BL32 will initialize the address space according to its |
| 21 | * own requirement. |
| 22 | */ |
| 23 | bl disable_mmu_icache_secure |
| 24 | stcopr r0, TLBIALL |
| 25 | dsb sy |
| 26 | isb |
| 27 | mov r0, r8 |
| 28 | bl bl2_el3_plat_prepare_exit |
| 29 | |
| 30 | /* |
| 31 | * Extract PC and SPSR based on struct `entry_point_info_t` |
| 32 | * and load it in LR and SPSR registers respectively. |
| 33 | */ |
| 34 | ldr lr, [r8, #ENTRY_POINT_INFO_PC_OFFSET] |
| 35 | ldr r1, [r8, #(ENTRY_POINT_INFO_PC_OFFSET + 4)] |
| 36 | msr spsr_xc, r1 |
| 37 | |
| 38 | /* Some BL32 stages expect lr_svc to provide the BL33 entry address */ |
| 39 | cps #MODE32_svc |
| 40 | ldr lr, [r8, #ENTRY_POINT_INFO_LR_SVC_OFFSET] |
| 41 | cps #MODE32_mon |
| 42 | |
| 43 | add r8, r8, #ENTRY_POINT_INFO_ARGS_OFFSET |
| 44 | ldm r8, {r0, r1, r2, r3} |
| 45 | exception_return |
| 46 | endfunc bl2_run_next_image |