Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | d741944 | 2020-01-27 15:38:26 -0600 | [diff] [blame] | 2 | * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 6 | #ifndef ARM_DEF_H |
| 7 | #define ARM_DEF_H |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 8 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <arch.h> |
| 10 | #include <common/interrupt_props.h> |
| 11 | #include <common/tbbr/tbbr_img_def.h> |
| 12 | #include <drivers/arm/gic_common.h> |
| 13 | #include <lib/utils_def.h> |
| 14 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Manish V Badarkhe | 5586151 | 2020-03-27 13:25:51 +0000 | [diff] [blame] | 15 | #include <plat/arm/common/smccc_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <plat/common/common_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | |
| 18 | /****************************************************************************** |
| 19 | * Definitions common to all ARM standard platforms |
| 20 | *****************************************************************************/ |
| 21 | |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 22 | /* |
| 23 | * Root of trust key hash lengths |
| 24 | */ |
| 25 | #define ARM_ROTPK_HEADER_LEN 19 |
| 26 | #define ARM_ROTPK_HASH_LEN 32 |
| 27 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 28 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 29 | #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 30 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 31 | #define ARM_SYSTEM_COUNT U(1) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 32 | |
| 33 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
| 34 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 35 | /* |
| 36 | * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The |
| 37 | * power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 38 | */ |
| 39 | #define ARM_PWR_LVL0 MPIDR_AFFLVL0 |
| 40 | #define ARM_PWR_LVL1 MPIDR_AFFLVL1 |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 41 | #define ARM_PWR_LVL2 MPIDR_AFFLVL2 |
Chandni Cherukuri | 9ec4a11 | 2018-10-16 14:42:19 +0530 | [diff] [blame] | 42 | #define ARM_PWR_LVL3 MPIDR_AFFLVL3 |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * Macros for local power states in ARM platforms encoded by State-ID field |
| 46 | * within the power-state parameter. |
| 47 | */ |
| 48 | /* Local power state for power domains in Run state. */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 49 | #define ARM_LOCAL_STATE_RUN U(0) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 50 | /* Local power state for retention. Valid only for CPU power domains */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 51 | #define ARM_LOCAL_STATE_RET U(1) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 52 | /* Local power state for OFF/power-down. Valid for CPU and cluster power |
| 53 | domains */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 54 | #define ARM_LOCAL_STATE_OFF U(2) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 55 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 56 | /* Memory location options for TSP */ |
| 57 | #define ARM_TRUSTED_SRAM_ID 0 |
| 58 | #define ARM_TRUSTED_DRAM_ID 1 |
| 59 | #define ARM_DRAM_ID 2 |
| 60 | |
| 61 | /* The first 4KB of Trusted SRAM are used as shared memory */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 62 | #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 63 | #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 64 | #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 65 | |
| 66 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 67 | #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ |
| 68 | ARM_SHARED_RAM_SIZE) |
| 69 | #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 70 | ARM_SHARED_RAM_SIZE) |
| 71 | |
| 72 | /* |
| 73 | * The top 16MB of DRAM1 is configured as secure access only using the TZC |
| 74 | * - SCP TZC DRAM: If present, DRAM reserved for SCP use |
| 75 | * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use |
| 76 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 77 | #define ARM_TZC_DRAM1_SIZE UL(0x01000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 78 | |
| 79 | #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 80 | ARM_DRAM1_SIZE - \ |
| 81 | ARM_SCP_TZC_DRAM1_SIZE) |
| 82 | #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE |
| 83 | #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ |
| 84 | ARM_SCP_TZC_DRAM1_SIZE - 1) |
| 85 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 86 | /* |
| 87 | * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime |
| 88 | * firmware. This region is meant to be NOLOAD and will not be zero |
| 89 | * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be |
| 90 | * placed here. |
| 91 | */ |
| 92 | #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 93 | #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 94 | #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ |
| 95 | ARM_EL3_TZC_DRAM1_SIZE - 1) |
| 96 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 97 | #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 98 | ARM_DRAM1_SIZE - \ |
| 99 | ARM_TZC_DRAM1_SIZE) |
| 100 | #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 101 | (ARM_SCP_TZC_DRAM1_SIZE + \ |
| 102 | ARM_EL3_TZC_DRAM1_SIZE)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 103 | #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ |
| 104 | ARM_AP_TZC_DRAM1_SIZE - 1) |
| 105 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 106 | /* Define the Access permissions for Secure peripherals to NS_DRAM */ |
| 107 | #if ARM_CRYPTOCELL_INTEG |
| 108 | /* |
| 109 | * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. |
| 110 | * This is required by CryptoCell to authenticate BL33 which is loaded |
| 111 | * into the Non Secure DDR. |
| 112 | */ |
| 113 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD |
| 114 | #else |
| 115 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE |
| 116 | #endif |
| 117 | |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 118 | #ifdef SPD_opteed |
| 119 | /* |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 120 | * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to |
| 121 | * load/authenticate the trusted os extra image. The first 512KB of |
| 122 | * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading |
| 123 | * for OPTEE is paged image which only include the paging part using |
| 124 | * virtual memory but without "init" data. OPTEE will copy the "init" data |
| 125 | * (from pager image) to the first 512KB of TZC_DRAM, and then copy the |
| 126 | * extra image behind the "init" data. |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 127 | */ |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 128 | #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
| 129 | ARM_AP_TZC_DRAM1_SIZE - \ |
| 130 | ARM_OPTEE_PAGEABLE_LOAD_SIZE) |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 131 | #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 132 | #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ |
| 133 | ARM_OPTEE_PAGEABLE_LOAD_BASE, \ |
| 134 | ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ |
| 135 | MT_MEMORY | MT_RW | MT_SECURE) |
Soby Mathew | 874fc9e | 2017-09-01 13:43:50 +0100 | [diff] [blame] | 136 | |
| 137 | /* |
| 138 | * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging |
| 139 | * support is enabled). |
| 140 | */ |
| 141 | #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ |
| 142 | BL32_BASE, \ |
| 143 | BL32_LIMIT - BL32_BASE, \ |
| 144 | MT_MEMORY | MT_RW | MT_SECURE) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 145 | #endif /* SPD_opteed */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 146 | |
| 147 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 148 | #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ |
| 149 | ARM_TZC_DRAM1_SIZE) |
| 150 | #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ |
| 151 | ARM_NS_DRAM1_SIZE - 1) |
| 152 | |
Sandrine Bailleux | 6c32fc7 | 2018-10-31 14:28:17 +0100 | [diff] [blame] | 153 | #define ARM_DRAM1_BASE ULL(0x80000000) |
| 154 | #define ARM_DRAM1_SIZE ULL(0x80000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 155 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ |
| 156 | ARM_DRAM1_SIZE - 1) |
| 157 | |
Sami Mujawar | a43ae7c | 2019-05-09 13:35:02 +0100 | [diff] [blame] | 158 | #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 159 | #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE |
| 160 | #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ |
| 161 | ARM_DRAM2_SIZE - 1) |
| 162 | |
| 163 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 164 | |
| 165 | #define ARM_IRQ_SEC_SGI_0 8 |
| 166 | #define ARM_IRQ_SEC_SGI_1 9 |
| 167 | #define ARM_IRQ_SEC_SGI_2 10 |
| 168 | #define ARM_IRQ_SEC_SGI_3 11 |
| 169 | #define ARM_IRQ_SEC_SGI_4 12 |
| 170 | #define ARM_IRQ_SEC_SGI_5 13 |
| 171 | #define ARM_IRQ_SEC_SGI_6 14 |
| 172 | #define ARM_IRQ_SEC_SGI_7 15 |
| 173 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 174 | /* |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 175 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 176 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 177 | * as Group 0 interrupts. |
| 178 | */ |
| 179 | #define ARM_G1S_IRQ_PROPS(grp) \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 180 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 181 | GIC_INTR_CFG_LEVEL), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 182 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 183 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 184 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 185 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 186 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 187 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 188 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 189 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 190 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 191 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 192 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 193 | GIC_INTR_CFG_EDGE) |
| 194 | |
| 195 | #define ARM_G0_IRQ_PROPS(grp) \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 196 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 197 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 198 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 199 | GIC_INTR_CFG_EDGE) |
| 200 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 201 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 202 | ARM_SHARED_RAM_BASE, \ |
| 203 | ARM_SHARED_RAM_SIZE, \ |
Juan Castillo | 2e86cb1 | 2016-01-13 15:01:09 +0000 | [diff] [blame] | 204 | MT_DEVICE | MT_RW | MT_SECURE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 205 | |
| 206 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 207 | ARM_NS_DRAM1_BASE, \ |
| 208 | ARM_NS_DRAM1_SIZE, \ |
| 209 | MT_MEMORY | MT_RW | MT_NS) |
| 210 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 211 | #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ |
| 212 | ARM_DRAM2_BASE, \ |
| 213 | ARM_DRAM2_SIZE, \ |
| 214 | MT_MEMORY | MT_RW | MT_NS) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 215 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 216 | #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ |
| 217 | TSP_SEC_MEM_BASE, \ |
| 218 | TSP_SEC_MEM_SIZE, \ |
| 219 | MT_MEMORY | MT_RW | MT_SECURE) |
| 220 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 221 | #if ARM_BL31_IN_DRAM |
| 222 | #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ |
| 223 | BL31_BASE, \ |
| 224 | PLAT_ARM_MAX_BL31_SIZE, \ |
| 225 | MT_MEMORY | MT_RW | MT_SECURE) |
| 226 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 227 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 228 | #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ |
| 229 | ARM_EL3_TZC_DRAM1_BASE, \ |
| 230 | ARM_EL3_TZC_DRAM1_SIZE, \ |
| 231 | MT_MEMORY | MT_RW | MT_SECURE) |
| 232 | |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 233 | #if defined(SPD_spmd) |
| 234 | #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ |
| 235 | PLAT_ARM_TRUSTED_DRAM_BASE, \ |
| 236 | PLAT_ARM_TRUSTED_DRAM_SIZE, \ |
| 237 | MT_MEMORY | MT_RW | MT_SECURE) |
| 238 | #endif |
| 239 | |
| 240 | |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 241 | /* |
John Tsichritzis | c34341a | 2018-07-30 13:41:52 +0100 | [diff] [blame] | 242 | * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to |
| 243 | * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides |
| 244 | * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order |
| 245 | * to be able to access the heap. |
| 246 | */ |
| 247 | #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ |
| 248 | BL1_RW_BASE, \ |
| 249 | BL1_RW_LIMIT - BL1_RW_BASE, \ |
| 250 | MT_MEMORY | MT_RW | MT_SECURE) |
| 251 | |
| 252 | /* |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 253 | * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section |
| 254 | * otherwise one region is defined containing both. |
| 255 | */ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 256 | #if SEPARATE_CODE_AND_RODATA |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 257 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 258 | BL_CODE_BASE, \ |
| 259 | BL_CODE_END - BL_CODE_BASE, \ |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 260 | MT_CODE | MT_SECURE), \ |
| 261 | MAP_REGION_FLAT( \ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 262 | BL_RO_DATA_BASE, \ |
| 263 | BL_RO_DATA_END \ |
| 264 | - BL_RO_DATA_BASE, \ |
| 265 | MT_RO_DATA | MT_SECURE) |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 266 | #else |
| 267 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
| 268 | BL_CODE_BASE, \ |
| 269 | BL_CODE_END - BL_CODE_BASE, \ |
| 270 | MT_CODE | MT_SECURE) |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 271 | #endif |
| 272 | #if USE_COHERENT_MEM |
| 273 | #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ |
| 274 | BL_COHERENT_RAM_BASE, \ |
| 275 | BL_COHERENT_RAM_END \ |
| 276 | - BL_COHERENT_RAM_BASE, \ |
| 277 | MT_DEVICE | MT_RW | MT_SECURE) |
| 278 | #endif |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 279 | #if USE_ROMLIB |
| 280 | #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ |
| 281 | ROMLIB_RO_BASE, \ |
| 282 | ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ |
| 283 | MT_CODE | MT_SECURE) |
| 284 | |
| 285 | #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ |
| 286 | ROMLIB_RW_BASE, \ |
| 287 | ROMLIB_RW_END - ROMLIB_RW_BASE,\ |
| 288 | MT_MEMORY | MT_RW | MT_SECURE) |
| 289 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 290 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 291 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 292 | * Map mem_protect flash region with read and write permissions |
| 293 | */ |
| 294 | #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ |
| 295 | V2M_FLASH_BLOCK_SIZE, \ |
| 296 | MT_DEVICE | MT_RW | MT_SECURE) |
| 297 | |
| 298 | /* |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 299 | * The max number of regions like RO(code), coherent and data required by |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 300 | * different BL stages which need to be mapped in the MMU. |
| 301 | */ |
Daniel Boulby | b1b058d | 2018-09-18 11:52:49 +0100 | [diff] [blame] | 302 | #define ARM_BL_REGIONS 5 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 303 | |
| 304 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ |
| 305 | ARM_BL_REGIONS) |
| 306 | |
| 307 | /* Memory mapped Generic timer interfaces */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 308 | #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) |
| 309 | #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) |
| 310 | #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) |
| 311 | #define ARM_SYS_CNT_BASE_S UL(0x2a820000) |
| 312 | #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 313 | |
| 314 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 315 | |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 316 | /* Trusted Watchdog constants */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 317 | #define ARM_SP805_TWDG_BASE UL(0x2a490000) |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 318 | #define ARM_SP805_TWDG_CLK_HZ 32768 |
| 319 | /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 |
| 320 | * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ |
| 321 | #define ARM_TWDG_TIMEOUT_SEC 128 |
| 322 | #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ |
| 323 | ARM_TWDG_TIMEOUT_SEC) |
| 324 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 325 | /****************************************************************************** |
| 326 | * Required platform porting definitions common to all ARM standard platforms |
| 327 | *****************************************************************************/ |
| 328 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 329 | /* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 330 | * This macro defines the deepest retention state possible. A higher state |
| 331 | * id will represent an invalid or a power down state. |
| 332 | */ |
| 333 | #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET |
| 334 | |
| 335 | /* |
| 336 | * This macro defines the deepest power down states possible. Any state ID |
| 337 | * higher than this is invalid. |
| 338 | */ |
| 339 | #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF |
| 340 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 341 | /* |
| 342 | * Some data must be aligned on the biggest cache line size in the platform. |
| 343 | * This is known only to the platform as it might have a combination of |
| 344 | * integrated and external caches. |
| 345 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 346 | #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 347 | |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 348 | /* |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 349 | * To enable FW_CONFIG to be loaded by BL1, define the corresponding base |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 350 | * and limit. Leave enough space of BL2 meminfo. |
| 351 | */ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 352 | #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 353 | #define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE) |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 354 | |
| 355 | /* |
| 356 | * Boot parameters passed from BL2 to BL31/BL32 are stored here |
| 357 | */ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 358 | #define ARM_BL2_MEM_DESC_BASE ARM_FW_CONFIG_LIMIT |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 359 | #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \ |
| 360 | (PAGE_SIZE / 2U)) |
| 361 | |
| 362 | /* |
| 363 | * Define limit of firmware configuration memory: |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 364 | * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 365 | */ |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 366 | #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 367 | |
| 368 | /******************************************************************************* |
| 369 | * BL1 specific defines. |
| 370 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 371 | * addresses. |
| 372 | ******************************************************************************/ |
| 373 | #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE |
| 374 | #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 375 | + (PLAT_ARM_TRUSTED_ROM_SIZE - \ |
| 376 | PLAT_ARM_MAX_ROMLIB_RO_SIZE)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 377 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 378 | * Put BL1 RW at the top of the Trusted SRAM. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 379 | */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 380 | #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ |
| 381 | ARM_BL_RAM_SIZE - \ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 382 | (PLAT_ARM_MAX_BL1_RW_SIZE +\ |
| 383 | PLAT_ARM_MAX_ROMLIB_RW_SIZE)) |
| 384 | #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ |
| 385 | (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) |
| 386 | |
| 387 | #define ROMLIB_RO_BASE BL1_RO_LIMIT |
| 388 | #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) |
| 389 | |
| 390 | #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) |
| 391 | #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 392 | |
| 393 | /******************************************************************************* |
| 394 | * BL2 specific defines. |
| 395 | ******************************************************************************/ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 396 | #if BL2_AT_EL3 |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 397 | /* Put BL2 towards the middle of the Trusted SRAM */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 398 | #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 399 | (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) |
Roberto Vargas | 5220780 | 2017-11-17 13:22:18 +0000 | [diff] [blame] | 400 | #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 401 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 402 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 403 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 404 | * Put BL2 just below BL1. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 405 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 406 | #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) |
| 407 | #define BL2_LIMIT BL1_RW_BASE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 408 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 409 | |
| 410 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 411 | * BL31 specific defines. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 412 | ******************************************************************************/ |
Madhukar Pappireddy | d741944 | 2020-01-27 15:38:26 -0600 | [diff] [blame] | 413 | #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 414 | /* |
| 415 | * Put BL31 at the bottom of TZC secured DRAM |
| 416 | */ |
| 417 | #define BL31_BASE ARM_AP_TZC_DRAM1_BASE |
| 418 | #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
| 419 | PLAT_ARM_MAX_BL31_SIZE) |
Madhukar Pappireddy | d741944 | 2020-01-27 15:38:26 -0600 | [diff] [blame] | 420 | /* |
| 421 | * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. |
| 422 | * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. |
| 423 | */ |
| 424 | #if SEPARATE_NOBITS_REGION |
| 425 | #define BL31_NOBITS_BASE BL2_BASE |
| 426 | #define BL31_NOBITS_LIMIT BL2_LIMIT |
| 427 | #endif /* SEPARATE_NOBITS_REGION */ |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 428 | #elif (RESET_TO_BL31) |
Manish Pandey | 2207e93 | 2019-11-06 13:17:46 +0000 | [diff] [blame] | 429 | /* Ensure Position Independent support (PIE) is enabled for this config.*/ |
| 430 | # if !ENABLE_PIE |
| 431 | # error "BL31 must be a PIE if RESET_TO_BL31=1." |
| 432 | #endif |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 433 | /* |
Soby Mathew | 68e6928 | 2018-12-12 14:13:52 +0000 | [diff] [blame] | 434 | * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely |
Soby Mathew | c5e1745 | 2019-01-07 14:07:58 +0000 | [diff] [blame] | 435 | * used for building BL31 and not used for loading BL31. |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 436 | */ |
Soby Mathew | c5e1745 | 2019-01-07 14:07:58 +0000 | [diff] [blame] | 437 | # define BL31_BASE 0x0 |
| 438 | # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 439 | #else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 440 | /* Put BL31 below BL2 in the Trusted SRAM.*/ |
| 441 | #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 442 | - PLAT_ARM_MAX_BL31_SIZE) |
| 443 | #define BL31_PROGBITS_LIMIT BL2_BASE |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 444 | /* |
| 445 | * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is |
| 446 | * because in the BL2_AT_EL3 configuration, BL2 is always resident. |
| 447 | */ |
| 448 | #if BL2_AT_EL3 |
| 449 | #define BL31_LIMIT BL2_BASE |
| 450 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 451 | #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 452 | #endif |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 453 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 454 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 455 | #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 456 | /******************************************************************************* |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 457 | * BL32 specific defines for EL3 runtime in AArch32 mode |
| 458 | ******************************************************************************/ |
| 459 | # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 460 | /* |
| 461 | * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding |
| 462 | * the page reserved for fw_configs) to BL32 |
| 463 | */ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 464 | # define BL32_BASE ARM_FW_CONFIGS_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 465 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 466 | # else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 467 | /* Put BL32 below BL2 in the Trusted SRAM.*/ |
| 468 | # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 469 | - PLAT_ARM_MAX_BL32_SIZE) |
| 470 | # define BL32_PROGBITS_LIMIT BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 471 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 472 | # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ |
| 473 | |
| 474 | #else |
| 475 | /******************************************************************************* |
| 476 | * BL32 specific defines for EL3 runtime in AArch64 mode |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 477 | ******************************************************************************/ |
| 478 | /* |
| 479 | * On ARM standard platforms, the TSP can execute from Trusted SRAM, |
| 480 | * Trusted DRAM (if available) or the DRAM region secured by the TrustZone |
| 481 | * controller. |
| 482 | */ |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 483 | # if SPM_MM |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 484 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 485 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) |
| 486 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 487 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 488 | ARM_AP_TZC_DRAM1_SIZE) |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 489 | # elif defined(SPD_spmd) |
| 490 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 491 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) |
| 492 | # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 493 | # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ |
| 494 | + (UL(1) << 21)) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 495 | # elif ARM_BL31_IN_DRAM |
| 496 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 497 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 498 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 499 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 500 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 501 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 502 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 503 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 504 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID |
| 505 | # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE |
| 506 | # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 507 | # define TSP_PROGBITS_LIMIT BL31_BASE |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 508 | # define BL32_BASE ARM_FW_CONFIGS_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 509 | # define BL32_LIMIT BL31_BASE |
| 510 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID |
| 511 | # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 512 | # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE |
| 513 | # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 514 | # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 515 | + (UL(1) << 21)) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 516 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID |
| 517 | # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE |
| 518 | # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE |
| 519 | # define BL32_BASE ARM_AP_TZC_DRAM1_BASE |
| 520 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 521 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 522 | # else |
| 523 | # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" |
| 524 | # endif |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 525 | #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 526 | |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 527 | /* |
| 528 | * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 529 | * SPD and no SPM-MM, as they are the only ones that can be used as BL32. |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 530 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 531 | #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 532 | # if defined(SPD_none) && !SPM_MM |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 533 | # undef BL32_BASE |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 534 | # endif /* defined(SPD_none) && !SPM_MM */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 535 | #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ |
Antonio Nino Diaz | e4fa370 | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 536 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 537 | /******************************************************************************* |
| 538 | * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. |
| 539 | ******************************************************************************/ |
| 540 | #define BL2U_BASE BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 541 | #define BL2U_LIMIT BL2_LIMIT |
| 542 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 543 | #define NS_BL2U_BASE ARM_NS_DRAM1_BASE |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 544 | #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 545 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 546 | /* |
| 547 | * ID of the secure physical generic timer interrupt used by the TSP. |
| 548 | */ |
| 549 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 550 | |
| 551 | |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 552 | /* |
| 553 | * One cache line needed for bakery locks on ARM platforms |
| 554 | */ |
| 555 | #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
| 556 | |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 557 | /* Priority levels for ARM platforms */ |
Jeenu Viswambharan | a5b5b8d | 2018-02-06 12:21:39 +0000 | [diff] [blame] | 558 | #define PLAT_RAS_PRI 0x10 |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 559 | #define PLAT_SDEI_CRITICAL_PRI 0x60 |
| 560 | #define PLAT_SDEI_NORMAL_PRI 0x70 |
| 561 | |
| 562 | /* ARM platforms use 3 upper bits of secure interrupt priority */ |
| 563 | #define ARM_PRI_BITS 3 |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 564 | |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 565 | /* SGI used for SDEI signalling */ |
| 566 | #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 |
| 567 | |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 568 | #if SDEI_IN_FCONF |
| 569 | /* ARM SDEI dynamic private event max count */ |
| 570 | #define ARM_SDEI_DP_EVENT_MAX_CNT 3 |
| 571 | |
| 572 | /* ARM SDEI dynamic shared event max count */ |
| 573 | #define ARM_SDEI_DS_EVENT_MAX_CNT 3 |
| 574 | #else |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 575 | /* ARM SDEI dynamic private event numbers */ |
| 576 | #define ARM_SDEI_DP_EVENT_0 1000 |
| 577 | #define ARM_SDEI_DP_EVENT_1 1001 |
| 578 | #define ARM_SDEI_DP_EVENT_2 1002 |
| 579 | |
| 580 | /* ARM SDEI dynamic shared event numbers */ |
| 581 | #define ARM_SDEI_DS_EVENT_0 2000 |
| 582 | #define ARM_SDEI_DS_EVENT_1 2001 |
| 583 | #define ARM_SDEI_DS_EVENT_2 2002 |
| 584 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 585 | #define ARM_SDEI_PRIVATE_EVENTS \ |
| 586 | SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ |
| 587 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 588 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 589 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
| 590 | |
| 591 | #define ARM_SDEI_SHARED_EVENTS \ |
| 592 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 593 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 594 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 595 | #endif /* SDEI_IN_FCONF */ |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 596 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 597 | #endif /* ARM_DEF_H */ |