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Nariman Poushin0ece80f2018-02-26 06:52:04 +00001/*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <platform_def.h>
Chandni Cherukuri82718852018-08-02 12:29:07 +053010#include <cortex_a75.h>
Deepak Pandeyb5615362018-10-11 13:44:43 +053011#include <cpu_macros.S>
Nariman Poushin0ece80f2018-02-26 06:52:04 +000012
Nariman Poushin0ece80f2018-02-26 06:52:04 +000013 .globl plat_arm_calc_core_pos
Chandni Cherukuri82718852018-08-02 12:29:07 +053014 .globl plat_reset_handler
Nariman Poushin0ece80f2018-02-26 06:52:04 +000015
16 /* -----------------------------------------------------
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053017 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
18 *
19 * Helper function to calculate the core position.
20 * (ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER * CSS_SGI_MAX_PE_PER_CPU) +
21 * (CPUId * CSS_SGI_MAX_PE_PER_CPU) +
22 * ThreadId
23 *
24 * which can be simplified as:
25 *
26 * ((ClusterId * CSS_SGI_MAX_CPUS_PER_CLUSTER + CPUId) *
27 * CSS_SGI_MAX_PE_PER_CPU) + ThreadId
28 * ------------------------------------------------------
29 */
30
Nariman Poushin0ece80f2018-02-26 06:52:04 +000031func plat_arm_calc_core_pos
Vishwanatha HG64f0b6f2018-05-08 17:15:37 +053032 mov x3, x0
33
34 /*
35 * The MT bit in MPIDR is always set for SGI platforms
36 * and the affinity level 0 corresponds to thread affinity level.
37 */
38
39 /* Extract individual affinity fields from MPIDR */
40 ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
41 ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
42 ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
43
44 /* Compute linear position */
45 mov x4, #CSS_SGI_MAX_CPUS_PER_CLUSTER
46 madd x1, x2, x4, x1
47 mov x5, #CSS_SGI_MAX_PE_PER_CPU
48 madd x0, x1, x5, x0
Nariman Poushin0ece80f2018-02-26 06:52:04 +000049 ret
50endfunc plat_arm_calc_core_pos
Chandni Cherukuri82718852018-08-02 12:29:07 +053051
Chandni Cherukuri82718852018-08-02 12:29:07 +053052 /* -----------------------------------------------------
53 * void plat_reset_handler(void);
54 *
55 * Determine the CPU MIDR and disable power down bit for
56 * that CPU.
57 * -----------------------------------------------------
58 */
59func plat_reset_handler
60 jump_if_cpu_midr CORTEX_A75_MIDR, A75
61 ret
62
63 /* -----------------------------------------------------
64 * Disable CPU power down bit in power control register
65 * -----------------------------------------------------
66 */
67A75:
68 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1
69 bic x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK
70 msr CORTEX_A75_CPUPWRCTLR_EL1, x0
71 isb
72 ret
73endfunc plat_reset_handler