Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 1 | # |
johpow01 | aef12f2 | 2020-10-15 13:40:04 -0500 | [diff] [blame] | 2 | # Copyright (c) 2021, Arm Limited. All rights reserved. |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 3 | # |
| 4 | # SPDX-License-Identifier: BSD-3-Clause |
| 5 | # |
| 6 | |
Andre Przywara | eec45eb | 2020-01-24 15:02:27 +0000 | [diff] [blame] | 7 | include lib/libfdt/libfdt.mk |
| 8 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 9 | RESET_TO_BL31 := 1 |
| 10 | ifeq (${RESET_TO_BL31}, 0) |
| 11 | $(error "This is a BL31-only port; RESET_TO_BL31 must be enabled") |
| 12 | endif |
| 13 | |
Oliver Swede | 3769b3f | 2019-12-16 14:08:27 +0000 | [diff] [blame] | 14 | ifeq (${ENABLE_PIE}, 1) |
| 15 | override SEPARATE_CODE_AND_RODATA := 1 |
| 16 | endif |
| 17 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 18 | CTX_INCLUDE_AARCH32_REGS := 0 |
| 19 | ifeq (${CTX_INCLUDE_AARCH32_REGS}, 1) |
| 20 | $(error "This is an AArch64-only port; CTX_INCLUDE_AARCH32_REGS must be disabled") |
| 21 | endif |
| 22 | |
| 23 | ifeq (${TRUSTED_BOARD_BOOT}, 1) |
| 24 | $(error "TRUSTED_BOARD_BOOT must be disabled") |
| 25 | endif |
| 26 | |
Andre Przywara | d9b95cc | 2020-07-08 13:01:00 +0100 | [diff] [blame] | 27 | PRELOADED_BL33_BASE := 0x80080000 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 28 | |
Andre Przywara | d9b95cc | 2020-07-08 13:01:00 +0100 | [diff] [blame] | 29 | FPGA_PRELOADED_DTB_BASE := 0x80070000 |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 30 | $(eval $(call add_define,FPGA_PRELOADED_DTB_BASE)) |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 31 | |
Andre Przywara | 0176793 | 2020-07-07 10:40:46 +0100 | [diff] [blame] | 32 | FPGA_PRELOADED_CMD_LINE := 0x1000 |
| 33 | $(eval $(call add_define,FPGA_PRELOADED_CMD_LINE)) |
| 34 | |
Tom Cosgrove | 2593a8a | 2021-08-17 08:50:53 +0100 | [diff] [blame] | 35 | ENABLE_AMU := 1 |
| 36 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 37 | # Treating this as a memory-constrained port for now |
| 38 | USE_COHERENT_MEM := 0 |
| 39 | |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 40 | # This can be overridden depending on CPU(s) used in the FPGA image |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 41 | HW_ASSISTED_COHERENCY := 1 |
| 42 | |
Andre Przywara | 8b50525 | 2020-04-09 10:10:09 +0100 | [diff] [blame] | 43 | PL011_GENERIC_UART := 1 |
| 44 | |
Javier Almansa Sobrino | e1ecd23 | 2020-08-20 18:48:09 +0100 | [diff] [blame] | 45 | SUPPORT_UNKNOWN_MPID ?= 1 |
| 46 | |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 47 | FPGA_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S |
| 48 | |
| 49 | # select a different set of CPU files, depending on whether we compile for |
| 50 | # hardware assisted coherency cores or not |
| 51 | ifeq (${HW_ASSISTED_COHERENCY}, 0) |
| 52 | # Cores used without DSU |
| 53 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ |
| 54 | lib/cpus/aarch64/cortex_a53.S \ |
| 55 | lib/cpus/aarch64/cortex_a57.S \ |
| 56 | lib/cpus/aarch64/cortex_a72.S \ |
| 57 | lib/cpus/aarch64/cortex_a73.S |
| 58 | else |
| 59 | # AArch64-only cores |
| 60 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ |
| 61 | lib/cpus/aarch64/cortex_a76ae.S \ |
| 62 | lib/cpus/aarch64/cortex_a77.S \ |
Jimmy Brisson | 7ec175e | 2020-06-01 16:49:34 -0500 | [diff] [blame] | 63 | lib/cpus/aarch64/cortex_a78.S \ |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 64 | lib/cpus/aarch64/neoverse_n_common.S \ |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 65 | lib/cpus/aarch64/neoverse_n1.S \ |
Javier Almansa Sobrino | 9faad3c | 2020-10-23 13:22:07 +0100 | [diff] [blame] | 66 | lib/cpus/aarch64/neoverse_n2.S \ |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 67 | lib/cpus/aarch64/neoverse_e1.S \ |
Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 68 | lib/cpus/aarch64/neoverse_v1.S \ |
Jimmy Brisson | 7cc90c4 | 2020-09-30 15:34:51 -0500 | [diff] [blame] | 69 | lib/cpus/aarch64/cortex_a78_ae.S \ |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 70 | lib/cpus/aarch64/cortex_a65.S \ |
Andre Przywara | cb16767 | 2020-06-25 13:10:38 +0100 | [diff] [blame] | 71 | lib/cpus/aarch64/cortex_a65ae.S \ |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 72 | lib/cpus/aarch64/cortex_a510.S \ |
| 73 | lib/cpus/aarch64/cortex_a710.S \ |
johpow01 | cd38ac4 | 2021-03-15 15:07:21 -0500 | [diff] [blame] | 74 | lib/cpus/aarch64/cortex_makalu.S \ |
johpow01 | 4c42c0d | 2021-04-20 17:05:04 -0500 | [diff] [blame] | 75 | lib/cpus/aarch64/cortex_makalu_elp_arm.S \ |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 76 | lib/cpus/aarch64/cortex_a78c.S |
Andre Przywara | cb16767 | 2020-06-25 13:10:38 +0100 | [diff] [blame] | 77 | |
Oliver Swede | 7fbb9b5 | 2020-01-15 10:20:09 +0000 | [diff] [blame] | 78 | # AArch64/AArch32 cores |
| 79 | FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ |
| 80 | lib/cpus/aarch64/cortex_a75.S |
| 81 | endif |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 82 | |
Javier Almansa Sobrino | e1ecd23 | 2020-08-20 18:48:09 +0100 | [diff] [blame] | 83 | ifeq (${SUPPORT_UNKNOWN_MPID}, 1) |
| 84 | # Add support for unknown/invalid MPIDs (aarch64 only) |
| 85 | $(eval $(call add_define,SUPPORT_UNKNOWN_MPID)) |
| 86 | FPGA_CPU_LIBS += lib/cpus/aarch64/generic.S |
| 87 | endif |
| 88 | |
Andre Przywara | e1cc130 | 2020-03-25 15:50:38 +0000 | [diff] [blame] | 89 | # Allow detection of GIC-600 |
| 90 | GICV3_SUPPORT_GIC600 := 1 |
Manish Pandey | b21cad7 | 2020-04-03 18:59:20 +0100 | [diff] [blame] | 91 | |
Andre Przywara | 42ba7c9 | 2021-05-18 15:53:05 +0100 | [diff] [blame] | 92 | GIC_ENABLE_V4_EXTN := 1 |
| 93 | |
Manish Pandey | b21cad7 | 2020-04-03 18:59:20 +0100 | [diff] [blame] | 94 | # Include GICv3 driver files |
| 95 | include drivers/arm/gic/v3/gicv3.mk |
| 96 | |
| 97 | FPGA_GIC_SOURCES := ${GICV3_SOURCES} \ |
Oliver Swede | b51da81 | 2019-12-03 14:08:21 +0000 | [diff] [blame] | 98 | plat/common/plat_gicv3.c \ |
| 99 | plat/arm/board/arm_fpga/fpga_gicv3.c |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 100 | |
Andre Przywara | eb5cb80 | 2020-08-03 12:54:58 +0100 | [diff] [blame] | 101 | FDT_SOURCES := fdts/arm_fpga.dts |
| 102 | |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 103 | PLAT_INCLUDES := -Iplat/arm/board/arm_fpga/include |
| 104 | |
| 105 | PLAT_BL_COMMON_SOURCES := plat/arm/board/arm_fpga/${ARCH}/fpga_helpers.S |
| 106 | |
Andre Przywara | eec45eb | 2020-01-24 15:02:27 +0000 | [diff] [blame] | 107 | BL31_SOURCES += common/fdt_wrappers.c \ |
Javier Almansa Sobrino | 3bcf3c8 | 2020-06-04 19:01:48 +0100 | [diff] [blame] | 108 | common/fdt_fixup.c \ |
Andre Przywara | eec45eb | 2020-01-24 15:02:27 +0000 | [diff] [blame] | 109 | drivers/delay_timer/delay_timer.c \ |
Oliver Swede | 8fed2fe | 2019-11-11 11:11:06 +0000 | [diff] [blame] | 110 | drivers/delay_timer/generic_delay_timer.c \ |
| 111 | drivers/arm/pl011/${ARCH}/pl011_console.S \ |
| 112 | plat/common/plat_psci_common.c \ |
| 113 | plat/arm/board/arm_fpga/fpga_pm.c \ |
| 114 | plat/arm/board/arm_fpga/fpga_topology.c \ |
| 115 | plat/arm/board/arm_fpga/fpga_console.c \ |
| 116 | plat/arm/board/arm_fpga/fpga_bl31_setup.c \ |
| 117 | ${FPGA_CPU_LIBS} \ |
| 118 | ${FPGA_GIC_SOURCES} |
| 119 | |
Andre Przywara | 586de5e | 2020-08-03 13:06:38 +0100 | [diff] [blame] | 120 | $(eval $(call MAKE_S,$(BUILD_PLAT),plat/arm/board/arm_fpga/rom_trampoline.S,31)) |
Andre Przywara | 6228e43 | 2020-09-16 17:13:33 +0100 | [diff] [blame] | 121 | $(eval $(call MAKE_LD,$(BUILD_PLAT)/build_axf.ld,plat/arm/board/arm_fpga/build_axf.ld.S,31)) |
| 122 | |
| 123 | bl31.axf: bl31 dtbs ${BUILD_PLAT}/rom_trampoline.o ${BUILD_PLAT}/build_axf.ld |
| 124 | $(ECHO) " LD $@" |
| 125 | $(Q)$(LD) -T ${BUILD_PLAT}/build_axf.ld -L ${BUILD_PLAT} --strip-debug -o ${BUILD_PLAT}/bl31.axf |
Andre Przywara | 586de5e | 2020-08-03 13:06:38 +0100 | [diff] [blame] | 126 | |
Andre Przywara | 6228e43 | 2020-09-16 17:13:33 +0100 | [diff] [blame] | 127 | all: bl31.axf |