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Nariman Poushinc703f902018-03-07 10:29:57 +00001#
Ambroise Vincent322971d2019-04-11 13:45:18 +01002# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Nariman Poushinc703f902018-03-07 10:29:57 +00003#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7CSS_SGM_BASE := plat/arm/css/sgm
8
9PLAT_INCLUDES := -I${CSS_SGM_BASE}/include
10
11PLAT_BL_COMMON_SOURCES := ${CSS_SGM_BASE}/sgm_mmap_config.c \
12 ${CSS_SGM_BASE}/aarch64/css_sgm_helpers.S
13
14SECURITY_SOURCES := drivers/arm/tzc/tzc_dmc500.c \
Ambroise Vincent322971d2019-04-11 13:45:18 +010015 plat/arm/common/arm_tzc_dmc500.c \
Nariman Poushinc703f902018-03-07 10:29:57 +000016 ${CSS_SGM_BASE}/sgm_security.c
17
18SGM_CPU_SOURCES := lib/cpus/aarch64/cortex_a55.S \
19 lib/cpus/aarch64/cortex_a75.S
20
21INTERCONNECT_SOURCES := ${CSS_SGM_BASE}/sgm_interconnect.c
22
23SGM_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
24 drivers/arm/gic/v3/gicv3_main.c \
25 drivers/arm/gic/v3/gicv3_helpers.c \
26 plat/common/plat_gicv3.c \
27 plat/arm/common/arm_gicv3.c \
28 drivers/arm/gic/v3/gic600.c \
29 drivers/arm/gic/v3/arm_gicv3_common.c
30
31BL1_SOURCES += $(SGM_CPU_SOURCES) \
32 ${INTERCONNECT_SOURCES} \
Ambroise Vincent322971d2019-04-11 13:45:18 +010033 ${CSS_SGM_BASE}/sgm_bl1_setup.c \
Nariman Poushinc703f902018-03-07 10:29:57 +000034 ${CSS_SGM_BASE}/sgm_plat_config.c
35
Ambroise Vincent322971d2019-04-11 13:45:18 +010036BL2_SOURCES += ${SECURITY_SOURCES} \
37 ${CSS_SGM_BASE}/sgm_plat_config.c
Nariman Poushinc703f902018-03-07 10:29:57 +000038
39BL2U_SOURCES += ${SECURITY_SOURCES}
40
41BL31_SOURCES += $(SGM_CPU_SOURCES) \
42 ${INTERCONNECT_SOURCES} \
43 ${SECURITY_SOURCES} \
44 ${SGM_GIC_SOURCES} \
Ambroise Vincent322971d2019-04-11 13:45:18 +010045 ${CSS_SGM_BASE}/sgm_topology.c \
Nariman Poushinc703f902018-03-07 10:29:57 +000046 ${CSS_SGM_BASE}/sgm_bl31_setup.c \
47 ${CSS_SGM_BASE}/sgm_plat_config.c
48
Deepak Pandeyb0971f92018-05-25 12:43:30 +053049ifneq (${RESET_TO_BL31},0)
Sandrine Bailleux1e32d322019-01-07 15:35:37 +010050 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Deepak Pandeyb0971f92018-05-25 12:43:30 +053051 Please set RESET_TO_BL31 to 0.")
52endif
53
Nariman Poushinc703f902018-03-07 10:29:57 +000054# sgm uses CCI-500 as Cache Coherent Interconnect
55ARM_CCI_PRODUCT_ID := 500
56
Nariman Poushinc703f902018-03-07 10:29:57 +000057# System coherency is managed in hardware
58HW_ASSISTED_COHERENCY := 1
59
60# When building for systems with hardware-assisted coherency, there's no need to
61# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
62USE_COHERENT_MEM := 0
63
64override ARM_PLAT_MT := 1
65
66$(eval $(call add_define,SGM_PLAT))
67
68include plat/arm/common/arm_common.mk
69include plat/arm/board/common/board_common.mk
70include plat/arm/css/common/css_common.mk
71include plat/arm/soc/common/soc_css.mk