Biwen Li | f553948 | 2021-03-08 11:42:11 +0800 | [diff] [blame] | 1 | # Copyright 2020-2022 NXP |
Jiafei Pan | 3f67d6e | 2021-01-05 17:17:15 +0800 | [diff] [blame] | 2 | # |
| 3 | # SPDX-License-Identifier: BSD-3-Clause |
| 4 | # |
| 5 | |
| 6 | # Adding SoC specific defines |
| 7 | |
| 8 | ifneq (${CACHE_LINE},) |
| 9 | $(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE})) |
| 10 | $(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE))))) |
| 11 | $(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE))) |
| 12 | endif |
| 13 | |
Biwen Li | f553948 | 2021-03-08 11:42:11 +0800 | [diff] [blame] | 14 | ifneq (${INTERCONNECT},) |
Jiafei Pan | 3f67d6e | 2021-01-05 17:17:15 +0800 | [diff] [blame] | 15 | $(eval $(call add_define,NXP_HAS_${INTERCONNECT})) |
Biwen Li | f553948 | 2021-03-08 11:42:11 +0800 | [diff] [blame] | 16 | ifeq (${INTERCONNECT}, CCI400) |
Jiafei Pan | 3f67d6e | 2021-01-05 17:17:15 +0800 | [diff] [blame] | 17 | ICNNCT_ID := 0x420 |
| 18 | $(eval $(call add_define,ICNNCT_ID)) |
| 19 | endif |
Jiafei Pan | 3f67d6e | 2021-01-05 17:17:15 +0800 | [diff] [blame] | 20 | endif |
| 21 | |
| 22 | ifneq (${CHASSIS},) |
| 23 | $(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS})) |
| 24 | endif |
| 25 | |
| 26 | ifneq (${PLAT_DDR_PHY},) |
| 27 | $(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY})) |
| 28 | endif |
| 29 | |
| 30 | ifneq (${PHYS_SYS},) |
| 31 | $(eval $(call add_define,CONFIG_PHYS_64BIT)) |
| 32 | endif |
| 33 | |
| 34 | ifneq (${CSF_HDR_SZ},) |
| 35 | $(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ})) |
| 36 | endif |
| 37 | |
| 38 | ifneq (${OCRAM_START_ADDR},) |
| 39 | $(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR})) |
| 40 | endif |
| 41 | |
| 42 | ifneq (${OCRAM_SIZE},) |
| 43 | $(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE})) |
| 44 | endif |
| 45 | |
| 46 | ifneq (${NXP_ROM_RSVD},) |
| 47 | $(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD})) |
| 48 | endif |
| 49 | |
| 50 | ifneq (${BL2_BASE},) |
| 51 | $(eval $(call add_define_val,BL2_BASE,${BL2_BASE})) |
| 52 | endif |
| 53 | |
| 54 | ifeq (${SEC_MEM_NON_COHERENT},yes) |
| 55 | $(eval $(call add_define,SEC_MEM_NON_COHERENT)) |
| 56 | endif |
| 57 | |
| 58 | ifneq (${NXP_ESDHC_ENDIANNESS},) |
| 59 | $(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS})) |
| 60 | endif |
| 61 | |
| 62 | ifneq (${NXP_SFP_VER},) |
| 63 | $(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER})) |
| 64 | endif |
| 65 | |
| 66 | ifneq (${NXP_SFP_ENDIANNESS},) |
| 67 | $(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS})) |
| 68 | endif |
| 69 | |
| 70 | ifneq (${NXP_GPIO_ENDIANNESS},) |
| 71 | $(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS})) |
| 72 | endif |
| 73 | |
| 74 | ifneq (${NXP_SNVS_ENDIANNESS},) |
| 75 | $(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS})) |
| 76 | endif |
| 77 | |
| 78 | ifneq (${NXP_GUR_ENDIANNESS},) |
| 79 | $(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS})) |
| 80 | endif |
| 81 | |
| 82 | ifneq (${NXP_FSPI_ENDIANNESS},) |
| 83 | $(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS})) |
| 84 | endif |
| 85 | |
| 86 | ifneq (${NXP_SEC_ENDIANNESS},) |
| 87 | $(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS})) |
| 88 | endif |
| 89 | |
| 90 | ifneq (${NXP_DDR_ENDIANNESS},) |
| 91 | $(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS})) |
| 92 | endif |
| 93 | |
| 94 | ifneq (${NXP_QSPI_ENDIANNESS},) |
| 95 | $(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS})) |
| 96 | endif |
| 97 | |
| 98 | ifneq (${NXP_SCFG_ENDIANNESS},) |
| 99 | $(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS})) |
| 100 | endif |
| 101 | |
| 102 | ifneq (${NXP_IFC_ENDIANNESS},) |
| 103 | $(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS})) |
| 104 | endif |
| 105 | |
| 106 | ifneq (${NXP_DDR_INTLV_256B},) |
| 107 | $(eval $(call add_define,NXP_DDR_INTLV_256B)) |
| 108 | endif |
| 109 | |
| 110 | ifneq (${PLAT_XLAT_TABLES_DYNAMIC},) |
| 111 | $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) |
| 112 | endif |
Jiafei Pan | 8dad316 | 2021-09-27 12:20:09 +0800 | [diff] [blame] | 113 | |
| 114 | ifeq (${OCRAM_ECC_EN},yes) |
| 115 | $(eval $(call add_define,CONFIG_OCRAM_ECC_EN)) |
| 116 | include ${PLAT_COMMON_PATH}/ocram/ocram.mk |
| 117 | endif |