Jiafei Pan | 3f67d6e | 2021-01-05 17:17:15 +0800 | [diff] [blame^] | 1 | # Copyright 2020-2021 NXP |
| 2 | # |
| 3 | # SPDX-License-Identifier: BSD-3-Clause |
| 4 | # |
| 5 | |
| 6 | # Adding SoC specific defines |
| 7 | |
| 8 | ifneq (${CACHE_LINE},) |
| 9 | $(eval $(call add_define_val,PLATFORM_CACHE_LINE_SHIFT,${CACHE_LINE})) |
| 10 | $(eval CACHE_WRITEBACK_GRANULE=$(shell echo $$((1 << $(CACHE_LINE))))) |
| 11 | $(eval $(call add_define_val,CACHE_WRITEBACK_GRANULE,$(CACHE_WRITEBACK_GRANULE))) |
| 12 | endif |
| 13 | |
| 14 | ifeq (${INTERCONNECT}, "CCI400") |
| 15 | $(eval $(call add_define,NXP_HAS_${INTERCONNECT})) |
| 16 | ICNNCT_ID := 0x420 |
| 17 | $(eval $(call add_define,ICNNCT_ID)) |
| 18 | endif |
| 19 | |
| 20 | ifeq (${INTERCONNECT}, "CCN508") |
| 21 | $(eval $(call add_define,NXP_HAS_CCN508)) |
| 22 | endif |
| 23 | |
| 24 | ifneq (${CHASSIS},) |
| 25 | $(eval $(call add_define,CONFIG_CHASSIS_${CHASSIS})) |
| 26 | endif |
| 27 | |
| 28 | ifneq (${PLAT_DDR_PHY},) |
| 29 | $(eval $(call add_define,NXP_DDR_${PLAT_DDR_PHY})) |
| 30 | endif |
| 31 | |
| 32 | ifneq (${PHYS_SYS},) |
| 33 | $(eval $(call add_define,CONFIG_PHYS_64BIT)) |
| 34 | endif |
| 35 | |
| 36 | ifneq (${CSF_HDR_SZ},) |
| 37 | $(eval $(call add_define_val,CSF_HDR_SZ,${CSF_HDR_SZ})) |
| 38 | endif |
| 39 | |
| 40 | ifneq (${OCRAM_START_ADDR},) |
| 41 | $(eval $(call add_define_val,NXP_OCRAM_ADDR,${OCRAM_START_ADDR})) |
| 42 | endif |
| 43 | |
| 44 | ifneq (${OCRAM_SIZE},) |
| 45 | $(eval $(call add_define_val,NXP_OCRAM_SIZE,${OCRAM_SIZE})) |
| 46 | endif |
| 47 | |
| 48 | ifneq (${NXP_ROM_RSVD},) |
| 49 | $(eval $(call add_define_val,NXP_ROM_RSVD,${NXP_ROM_RSVD})) |
| 50 | endif |
| 51 | |
| 52 | ifneq (${BL2_BASE},) |
| 53 | $(eval $(call add_define_val,BL2_BASE,${BL2_BASE})) |
| 54 | endif |
| 55 | |
| 56 | ifeq (${SEC_MEM_NON_COHERENT},yes) |
| 57 | $(eval $(call add_define,SEC_MEM_NON_COHERENT)) |
| 58 | endif |
| 59 | |
| 60 | ifneq (${NXP_ESDHC_ENDIANNESS},) |
| 61 | $(eval $(call add_define,NXP_ESDHC_${NXP_ESDHC_ENDIANNESS})) |
| 62 | endif |
| 63 | |
| 64 | ifneq (${NXP_SFP_VER},) |
| 65 | $(eval $(call add_define,NXP_SFP_VER_${NXP_SFP_VER})) |
| 66 | endif |
| 67 | |
| 68 | ifneq (${NXP_SFP_ENDIANNESS},) |
| 69 | $(eval $(call add_define,NXP_SFP_${NXP_SFP_ENDIANNESS})) |
| 70 | endif |
| 71 | |
| 72 | ifneq (${NXP_GPIO_ENDIANNESS},) |
| 73 | $(eval $(call add_define,NXP_GPIO_${NXP_GPIO_ENDIANNESS})) |
| 74 | endif |
| 75 | |
| 76 | ifneq (${NXP_SNVS_ENDIANNESS},) |
| 77 | $(eval $(call add_define,NXP_SNVS_${NXP_SNVS_ENDIANNESS})) |
| 78 | endif |
| 79 | |
| 80 | ifneq (${NXP_GUR_ENDIANNESS},) |
| 81 | $(eval $(call add_define,NXP_GUR_${NXP_GUR_ENDIANNESS})) |
| 82 | endif |
| 83 | |
| 84 | ifneq (${NXP_FSPI_ENDIANNESS},) |
| 85 | $(eval $(call add_define,NXP_FSPI_${NXP_FSPI_ENDIANNESS})) |
| 86 | endif |
| 87 | |
| 88 | ifneq (${NXP_SEC_ENDIANNESS},) |
| 89 | $(eval $(call add_define,NXP_SEC_${NXP_SEC_ENDIANNESS})) |
| 90 | endif |
| 91 | |
| 92 | ifneq (${NXP_DDR_ENDIANNESS},) |
| 93 | $(eval $(call add_define,NXP_DDR_${NXP_DDR_ENDIANNESS})) |
| 94 | endif |
| 95 | |
| 96 | ifneq (${NXP_QSPI_ENDIANNESS},) |
| 97 | $(eval $(call add_define,NXP_QSPI_${NXP_QSPI_ENDIANNESS})) |
| 98 | endif |
| 99 | |
| 100 | ifneq (${NXP_SCFG_ENDIANNESS},) |
| 101 | $(eval $(call add_define,NXP_SCFG_${NXP_SCFG_ENDIANNESS})) |
| 102 | endif |
| 103 | |
| 104 | ifneq (${NXP_IFC_ENDIANNESS},) |
| 105 | $(eval $(call add_define,NXP_IFC_${NXP_IFC_ENDIANNESS})) |
| 106 | endif |
| 107 | |
| 108 | ifneq (${NXP_DDR_INTLV_256B},) |
| 109 | $(eval $(call add_define,NXP_DDR_INTLV_256B)) |
| 110 | endif |
| 111 | |
| 112 | ifneq (${PLAT_XLAT_TABLES_DYNAMIC},) |
| 113 | $(eval $(call add_define,PLAT_XLAT_TABLES_DYNAMIC)) |
| 114 | endif |