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Rex-BC Chenb48c6c42021-04-12 11:10:31 +08001/*
developerec6eef72022-07-11 18:48:43 +08002 * Copyright (c) 2020-2022, MediaTek Inc. All rights reserved.
Rex-BC Chenb48c6c42021-04-12 11:10:31 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
Madhukar Pappireddya2e3a0c2021-11-11 11:32:53 -06006
7#include <inttypes.h>
8
Rex-BC Chenb48c6c42021-04-12 11:10:31 +08009#include <common/debug.h>
10#include <lib/mmio.h>
11#include <mt_dp.h>
12#include <mtk_sip_svc.h>
13#include <platform_def.h>
14
15static uint32_t dp_write_sec_reg(uint32_t is_edp, uint32_t offset,
16 uint32_t value, uint32_t mask)
17{
developer479d1ad2022-07-12 10:24:26 +080018 uint32_t reg = (is_edp != 0U) ? EDP_SEC_BASE : DP_SEC_BASE;
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080019
20 mmio_clrsetbits_32(reg + offset, mask, value);
21
22 return mmio_read_32(reg + offset);
23}
24
25int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val)
26{
27 int32_t ret = 0L;
28 uint32_t is_edp = 0UL;
29 uint32_t regval = 0UL;
30 uint32_t regmsk = 0UL;
31 uint32_t fldmask = 0UL;
32
33 if ((cmd > DP_ATF_CMD_COUNT) || (val == NULL)) {
Madhukar Pappireddya2e3a0c2021-11-11 11:32:53 -060034 INFO("dp_secure_handler error cmd 0x%" PRIx64 "\n", cmd);
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080035 return MTK_SIP_E_INVALID_PARAM;
36 }
37
38 switch (cmd) {
39 case DP_ATF_DP_VIDEO_UNMUTE:
40 INFO("[%s] DP_ATF_DP_VIDEO_UNMUTE\n", __func__);
41 is_edp = DP_ATF_TYPE_DP;
42 ret = MTK_SIP_E_SUCCESS;
43 break;
44 case DP_ATF_EDP_VIDEO_UNMUTE:
45 INFO("[%s] DP_ATF_EDP_VIDEO_UNMUTE\n", __func__);
46 is_edp = DP_ATF_TYPE_EDP;
47 ret = MTK_SIP_E_SUCCESS;
48 break;
49 default:
50 ret = MTK_SIP_E_INVALID_PARAM;
51 break;
52 }
53
54 if (ret == MTK_SIP_E_SUCCESS) {
55 regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK |
developer7fa15de2022-07-11 19:03:35 +080056 VIDEO_MUTE_SW_SECURE_FLDMASK);
Rex-BC Chenb48c6c42021-04-12 11:10:31 +080057 if (para > 0U) {
58 fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK;
59 } else {
60 fldmask = 0;
61 }
62
63 regval = (VIDEO_MUTE_SEL_SECURE_FLDMASK | fldmask);
64 *val = dp_write_sec_reg(is_edp, DP_TX_SECURE_REG11,
65 regval, regmsk);
66 }
67
68 return ret;
69}
developer7fa15de2022-07-11 19:03:35 +080070
71u_register_t mtk_dp_sip_handler(u_register_t x1, u_register_t x2,
72 u_register_t x3, u_register_t x4,
73 void *handle, struct smccc_res *smccc_ret)
74{
75 uint32_t ret_val;
76
77 return dp_secure_handler(x1, x2, &ret_val);
78}
79DECLARE_SMC_HANDLER(MTK_SIP_DP_CONTROL, mtk_dp_sip_handler);