Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 1 | /* |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 2 | * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 9 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/debug.h> |
| 13 | #include <drivers/delay_timer.h> |
| 14 | #include <lib/mmio.h> |
| 15 | #include <lib/utils_def.h> |
| 16 | #include <plat/common/platform.h> |
| 17 | |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 18 | #include <sunxi_cpucfg.h> |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 19 | #include <sunxi_mmap.h> |
Andre Przywara | 456208a | 2018-10-14 12:02:02 +0100 | [diff] [blame] | 20 | #include <sunxi_private.h> |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 21 | |
Samuel Holland | 7318655 | 2021-01-24 17:06:54 -0600 | [diff] [blame^] | 22 | #ifndef SUNXI_CPUIDLE_EN_REG |
| 23 | #include <core_off_arisc.h> |
| 24 | #endif |
| 25 | |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 26 | static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core) |
| 27 | { |
| 28 | if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff) |
| 29 | return; |
| 30 | |
Andre Przywara | 8501d09 | 2018-06-22 01:33:34 +0100 | [diff] [blame] | 31 | VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core); |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 32 | |
| 33 | mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff); |
| 34 | } |
| 35 | |
| 36 | static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core) |
| 37 | { |
| 38 | if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0) |
| 39 | return; |
| 40 | |
Andre Przywara | 8501d09 | 2018-06-22 01:33:34 +0100 | [diff] [blame] | 41 | VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core); |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 42 | |
| 43 | /* Power enable sequence from original Allwinner sources */ |
| 44 | mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe); |
| 45 | mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8); |
| 46 | mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0); |
| 47 | mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80); |
| 48 | mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00); |
| 49 | } |
| 50 | |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 51 | /* We can't turn ourself off like this, but it works for other cores. */ |
| 52 | static void sunxi_cpu_off(u_register_t mpidr) |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 53 | { |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 54 | unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); |
| 55 | unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 56 | |
Andre Przywara | 8501d09 | 2018-06-22 01:33:34 +0100 | [diff] [blame] | 57 | VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core); |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 58 | |
| 59 | /* Deassert DBGPWRDUP */ |
| 60 | mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 61 | /* Activate the core output clamps, but not for core 0. */ |
| 62 | if (core != 0) |
| 63 | mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); |
| 64 | /* Assert CPU power-on reset */ |
| 65 | mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); |
| 66 | /* Remove power from the CPU */ |
| 67 | sunxi_cpu_disable_power(cluster, core); |
| 68 | } |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 69 | |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 70 | void sunxi_cpu_power_off_self(void) |
| 71 | { |
| 72 | u_register_t mpidr = read_mpidr(); |
| 73 | unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 74 | |
| 75 | /* Simplifies assembly, all SoCs so far are single cluster anyway. */ |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 76 | assert(MPIDR_AFFLVL1_VAL(mpidr) == 0); |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 77 | |
Samuel Holland | 7318655 | 2021-01-24 17:06:54 -0600 | [diff] [blame^] | 78 | #ifdef SUNXI_CPUIDLE_EN_REG |
| 79 | /* Enable the CPUIDLE hardware (only really needs to be done once). */ |
| 80 | mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0x16aa0000); |
| 81 | mmio_write_32(SUNXI_CPUIDLE_EN_REG, 0xaa160001); |
| 82 | |
| 83 | /* Trigger power off for this core. */ |
| 84 | mmio_write_32(SUNXI_CORE_CLOSE_REG, BIT_32(core)); |
| 85 | #else |
Andre Przywara | 6d0b81b | 2018-09-28 00:43:32 +0100 | [diff] [blame] | 86 | /* |
| 87 | * If we are supposed to turn ourself off, tell the arisc SCP |
| 88 | * to do that work for us. The code expects the core mask to be |
| 89 | * patched into the first instruction. |
| 90 | */ |
| 91 | sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off), |
Samuel Holland | ac684b9 | 2019-10-20 14:18:48 -0500 | [diff] [blame] | 92 | BIT_32(core)); |
Samuel Holland | 7318655 | 2021-01-24 17:06:54 -0600 | [diff] [blame^] | 93 | #endif |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 94 | } |
| 95 | |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 96 | void sunxi_cpu_on(u_register_t mpidr) |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 97 | { |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 98 | unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr); |
| 99 | unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); |
| 100 | |
Andre Przywara | 8501d09 | 2018-06-22 01:33:34 +0100 | [diff] [blame] | 101 | VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core); |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 102 | |
| 103 | /* Assert CPU core reset */ |
| 104 | mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); |
| 105 | /* Assert CPU power-on reset */ |
| 106 | mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); |
| 107 | /* Set CPU to start in AArch64 mode */ |
| 108 | mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); |
| 109 | /* Apply power to the CPU */ |
| 110 | sunxi_cpu_enable_power(cluster, core); |
| 111 | /* Release the core output clamps */ |
| 112 | mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core)); |
| 113 | /* Deassert CPU power-on reset */ |
| 114 | mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); |
| 115 | /* Deassert CPU core reset */ |
| 116 | mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core)); |
| 117 | /* Assert DBGPWRDUP */ |
| 118 | mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core)); |
| 119 | } |
| 120 | |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 121 | void sunxi_cpu_power_off_others(void) |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 122 | { |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 123 | u_register_t self = read_mpidr(); |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 124 | unsigned int cluster; |
| 125 | unsigned int core; |
| 126 | |
| 127 | for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) { |
| 128 | for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) { |
| 129 | u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) | |
| 130 | (core << MPIDR_AFF0_SHIFT) | |
| 131 | BIT(31); |
Samuel Holland | 91bcab9 | 2021-01-24 06:37:29 -0600 | [diff] [blame] | 132 | if (mpidr != self) |
Samuel Holland | c629daf | 2019-02-17 15:33:33 -0600 | [diff] [blame] | 133 | sunxi_cpu_off(mpidr); |
| 134 | } |
Samuel Holland | 321c0ab | 2017-08-12 04:07:39 -0500 | [diff] [blame] | 135 | } |
| 136 | } |